Askaryan Radio Array (ARA) Readout

ARA Readout overview

Deployment Google docs (8-AUG-2011)   [link]

Design Reference Page [yr2 link]

15-JAN-2013 == meeting restart?

If anyone wants to call in:  (808) 956-2920 (single line, first come, first serve)

 Agenda:

1 - AMBER (to be covered in the morning Amber meeting, I think)

2 - ARA

     A - assembly (Travis/Brian/Brendan/Windell)

          - pre-amps ........................ done
          - downhole optical zonus .... 2 assembled; others to be assembled this week (Christian/Windell/Brian)
          - receivers (FOAM) ............. 5 boxes ready
          - power box ....................... need to trim the 12V supply under load; need to write email/elog about wiring scheme; need to cold-test
          - DAQ box ......................... Moxa, Rb+clock+2 TTL boosts in place, deep antenna input chain in place; wiring to do still (Brian/Windell/Brendan)
          - power->DAQ box cable ....  done
          - 300V->power box cable .... done
          - 2 DAQ box power cables .. needed for testing

     B - cold testing of complete components

          - pre-amps ......................... 17 done ... need to check if the two removed LARK filters are in spec
          - downhole optical zonus ....  2 done over the weekend; awaiting assembly of others
          - receivers (FOAM) ............. 3 boxes done, 2 more to go
          - power box ........................
          - DAQ box ..........................

     C - antennae (Peter/Christian/Brian)

     D - shipping for deployment [arrive at Pole by Dec 10] (everyone)

          THURSDAY: pack preamps, downhole zonus, receivers, power box, 300V power supply, test equipment
          FRIDAY: ship to Pole

     E - DAQ system (Brendan/Windell/Ben/Luca)

          - DDA_EVAL ....................... working: can read/write to DDA & read out a pedestal trigger from DDA
          - surface TDA status ............ need to test with surface preamps+receiver using DDA_EVAL board
          - AT-AT temperature board .... cold-tested; works as advertised
          - ATRI status/firmware
            . ATRI board ..................... x-ray Hawaii-01 (the one that worked) and ATRI-09 (a new one from Sierra that does not work) boards
          - ICRR status
            . SBC ............................... ARA2 operating system runs, was able to load the FPGA on the ICRR, and was able to read board id and version registers
            . ICRR board ..................... trigger: have checked the diode trigger inputs (all good, see clean, +225 mV signals from VAM-6 for SNR ~10 input signals)
                                                                have switched batwing trigger inputs to diode triggers; tested to see +225 mV signals from VAM-6 for SNR ~10 input signals
                                                      signal: checked all rf signal inputs - all now good; switched capacitors on batwing channels 5-8 to lower low-end of high-pass filter
                                                      FPGA: have switched batwing (+/-) trigger to discone (+) only triggers
                                                                 replaced trigger algorithm with 5/12 deep & 3/4 surface; see waveforms in proper places for surface and deep triggered events
                                                                 need to fix the SMB trigger so that it reads out the proper time window when there's a trigger and does not break the rf trigger time window
            . calpulser interface ........... Diolan USB<->I2C (3.3V) translator cold-tested with AT-AT temperature board; no problems seen; need to discuss wiring for I2C bus with Patrick
            . GPS .............................. need a 3.3/5V -> 3V power regulator - Windell purchased one

     F - calibration pulser

          - control board .................... received boards back from Patrick; need to test new pulser
          - deep board ....................... instructions for testing from Kara; need to finish power box & DAQ box and then test
          - surface cal board .............. awaiting arrival of a spare calpulser surface board for working with deep board after power box goes to Pole

     G - cables (Travis/Ben/Windell)

          - LMR-610 .......................... ELOG done with S12 & TDR measurements (shipped to Pole)
          - 6m Helix .......................... S12 & TDR measurements done, data needs to put on ELOG (shipped to Pole)
          - downhole fiber .................. S12 & Power measurements done - one poor fiber, all else okay

     H - surface antenna integration (Peter/Travis/Brendan/Luca)

. Preamps ..................................... tested warm (noise meter & network analyzer; setting filter window) - will need to be lock-tighted, etc. later
. Receiver box ............................... tested warm (with pulser pulser)
. Power detectors .......................... tested; redoing wiring (switch to Teflon/twist pairs) as prep for placement in DAQ box
. V0 Surface TDA .......................... can set DACs; card is probably not useable: threshold to close to edge of card; also surface combinatoric trigger signal not seen with pulser so firmware needs a fix
. V1 Surface TDA .......................... testing on DDA_EVAL

3 - ANITA3 hardware development (main meeting: moved to Wednesdays)

     A - Firmware Update (Lisa)
          1. Xilinx eval board Implementation check status? (w/Luca)
     B - ASICs updates (Gary)
          1. LAB4 are in hand (eval board - Gary start - Zhe finish?)
          2. RITC are in hand (eval board - Kurtis start - Zhe finish?)
          3. ARM silicon compilation check IBM 130nm (Lisa/Luca)
    C - SURF/TURF plans (Zhe Cao arrived)
4 - EVA placeholder

5 - All other business

22-NOV-2011 13:30 -- note unusual time (local Radio meeting):


1 - AMBER update [pdf]   (Rishi & Patrick in Argentina/Roberto?)

2 - ARA

     A - testing the pieces in the Freezer (Brendan/Ben)

          - LARK notched filters ......... 21 tested and good
          - LARK not-notched filters ... 19 (maybe 20) tested
          - optical zonus ................... 15 good cold tested, 1 warm tested good, 1 of 16 good ones found bad when retested on many Sundays ago
          - ATRI board ...................... 

     B - assembly (Travis/Brian/Brendan/Windell)

          - pre-amps ........................ done
          - downhole optical zonus .... 1 assembled; others to be assembled this week (Christian)
          - receivers (FOAM) ............ 4 boxes ready & 1 awaiting 5dB attenuator
          - power box ....................... all power supplies in place; warm-tested; need to finish wiring the calibration pulser control lines
          - DAQ box ......................... supports for Moxa, Rb+clock+2 TTL boosts in place, 1/2 deep antenna input chain in place; wiring to do still (Brian/Windell/Brendan)
          - power->DAQ box cable ....  done
          - 300V->power box cable .... done

     C - cold testing of complete components

          - pre-amps ......................... done ... need to check if the two removed LARK filters are in spec
          - downhole optical zonus ....
          - receivers (FOAM) ............. 3 boxes, 2 more to go
          - power box ........................
          - DAQ box .........................

     D - DAQ system (Brendan/Windell/Ben/Luca)

          - DDA_EVAL ....................... working: can read/write to DDA & read out a pedestal trigger from DDA
          - DDA status ....................... need to replace WF2 connectors with WF connects; need to clean Samtec connectors; need to return bad LS bit DDA' to Patrick 
          - TDA status ....................... all four channels work; see expected gain
                                                     TO DO: - need to replace power overload sense resistors
                                                                 - have threshold curves for 3 out of 4 TDAs using 5 dB attenuators; need to do threshold curves for 1 TDAs; need to decide upon input attenuation
          - surface TDA status ........... ARAacqd software now able to control DAC & do threshold scans
          - temperature board ............. received from Patrick, will be tested after being integrated into DAQ box
          - ATRI status/firmware
            . SBC ............................... OSU one crashes rather often too
                                                      locks up rather more often than not, usually during a read to the flash card
            . ATRI board ..................... FX2 (Cypress) chip death - replaced FX2 on Hawaii-01 board, SBC still does not see the FX2
                                                                                              replaced transistor fix (since I burned it out), but oscillator now dead 
            . FPGA ............................. continuing to debug the event readout
                                                      - self-triggered data exhibits one time-bin spikes and dips when trigger rate rises above ~2 to 20 Hz (CAUSE: blocking IRS readout for order ms)
                                                      - trigger readout is limited to 2Hz for some as-yet-unknown reason (CAUSE: threading issue in ARAAcqd)
                                                      - low 'first block' in event data (CAUSE: transitions in signals)
                                                      - odd fluctations around block 20 in event data (CAUSE: pick up from too many simultaneous transitions)
                                                      STILL OPEN:
                                                      - addition of a 'reset' method to firmware for clean start up of FPGA+FX2
                                                      - test updated FX2 firmware from Jonathan - second update to be tested
                                                      - started integrating & testing surface trigger: v0 card doesn't meet our needs; v1 card arrived from Uwe; combinatoric trigger not seen in Chipscope
             . ARAAcqd ...................... update needed for proper surface trigger threshold scan 
             . calibration data-taking ..... Vadj scan done, but other data will not be collected before DAQ assembly due to ATRI board death
          - ICRR status
            . SBC ............................... ARA2 operating system runs, was able to load the FPGA on the ICRR, and was able to read board id and version registers
            . ICRR board ..................... trigger: checked the diode trigger inputs (all good, see clean, +225 mV signals from VAM-6 for SNR ~10 input signals)
                                                                 switched batwing trigger inputs to diode triggers; tested to see +225 mV signals from VAM-6 for SNR ~10 input signals
                                                      signal: checked all rf signal inputs - all now good; switched capacitors on batwing channels 5-8 to lower low-end of high-pass filter
                                                      FPGA: switched batwing (+/-) trigger to discone (+) only triggers
                                                                 replaced trigger algorithm with 5/12 deep & 3/4 surface; need to test surface part of this trigger
                                                                 need to fix the SMB trigger so that it reads out the proper time window when there's a trigger and does not break the rf trigger time window
            . calpulser interface ........... talking with Ryan, Jonathan, and Patrick about a USB<->I2C (3.3V) converter
            . GPS .............................. need 3.3/5V -> 3V power regulator 

     E - calibration pulser

          - control board .................... received boards back from Patrick, need to test new pulser
          - deep board ....................... instructions for testing from Kara, need to finish power box & DAQ box and then test

     F - cables (Travis/Ben/Windell)

          - LMR-610 .......................... ELOG done with S12 & TDR measurements (shipped to Pole)
          - 6m Helix .......................... S12 & TDR measurements done, data needs to put on ELOG (shipped to Pole)
          - downhole fiber .................. S12 & Power measurements done - one poor fiber, all else okay

     G - surface antenna integration (Peter/Travis/Brendan/Luca)

. Preamps ..................................... tested warm (noise meter & network analyzer; setting filter window) - will need to be lock-tighted, etc. later
. Receiver box ............................... tested warm (with pulser pulser)
. Power detectors .......................... tested; redoing wiring (switch to Teflon/twist pairs) as prep for placement in DAQ box
. V0 Surface TDA .......................... can set DACs; card is probably not useable: threshold to close to edge of card; also surface combinatoric trigger signal not seen with pulser so firmware needs a fix
. V1 Surface TDA .......................... testing on DDA_EVAL

     H - antennae (Peter/Christian/Brian)
     I - shipping

3 - ANITA3 hardware development (main meeting: moved to Wednesdays)

     A - Firmware Update (Lisa)
          1. Xilinx eval board Implementation check status? (w/Luca)
     B - ASICs updates (Gary)
          1. LAB4 are in hand (eval board - Gary start - Zhe finish?)
          2. RITC are in hand (eval board - Kurtis start - Zhe finish?)
          3. ARM silicon compilation check IBM 130nm (Lisa/Luca)
    C - SURF/TURF plans

4 - EVA placeholder

5 - All other business

7-NOV-2011 11am? (local Radio meeting):

Due to faculty candidate Special Colloquium at 3:30pm this afternoon, we'll hold the weekly meeting after the ANITA phone call ends ... if anyone
wants to call in, the phone number is:

                                                        (808) 956-2920

Note that this phone is only one line, so it is availability is first come/first served. 

Agenda:

1 - AMBER (Rishi in Argentina/Roberto)  [PDF]

2 - ARA

     A - building the various enclosures (Christian/Brian)

          - pre-amps ........................... done
          - downhole optical zonus ....... finished ... returned from iriditing
          - receiver boxes ................... done
          - power box ......................... done
          - DAQ box ........................... done

     B - testing the pieces in the Freezer (Brendan/Ben)

          - LARK notched filters ......... 21 tested and good
          - LARK not-notched filters ... 19 (maybe 20) tested
          - optical zonus ................... 15 good cold tested, 1 warm tested good, 1 of 16 good ones found bad when retested on Sunday
          - ATRI board ...................... 

     C - assembly (Travis)

          - pre-amps ........................ assembled, tested warm, 17 tested cold ... switched out 2 LARK filters to improve noise curve; need to see if rejects ones within specs
          - downhole optical zonus .... ready for assembly (Brian/Christian/Travis)
          - receivers (FOAM) ............ 4 box ready & warm tested with network analyzer, awaiting gaskets to complete task; cold tested one receiver box (Travis/Brian/Brendan)
          - power box ....................... all power supplies in place; calibration cards in place; awaiting gaskets to complete task
          - DAQ box ......................... supports for Moxa and deep antenna input chain being fabricated, support for Rb clock+2 TTL boosts to be designed; aim: get this done now (Brian/Windell/Brendan)
          - power->DAQ box cable ..... two cables ready (Brian)

     D - DAQ system (Brendan/Ben/Luca)

          - DDA_EVAL ....................... working: can read/write to DDA & read out a pedestal trigger from DDA
          - DDA status ....................... need to replace WF2 connectors with WF connects; need to clean Samtec connectors; need to return bad LS bit DDA' to Patrick 
          - TDA status ....................... all four channels work; see expected gain
                                                     TO DO: - need to replace power overload sense resistors
                                                                 - have threshold curves for 3 out of 4 TDAs using 5 dB attenuators; need to do threshold curves for 1 TDAs; need to decide upon input attenuation
          - surface TDA status ........... ARAacqd software now able to control DAC & do threshold scans
          - temperature board ............. received from Patrick, will be tested after being integrated into DAQ box
          - ATRI status/firmware
            . SBC ............................... OSU one crashes rather often too
                                                      locks up rather more often than not, usually during a read to the flash card
            . ATRI board ..................... FX2 (Cypress) chip death - replaced FX2 on Hawaii-01 board, SBC still does see the FX2
                                                                                              replaced transistor fix (since I burned it out), will check to see if FX2 becomes visible
            . FPGA ............................. continuing to debug the event readout
                                                      - self-triggered data exhibits one time-bin spikes and dips when trigger rate rises above ~2 to 20 Hz (CAUSE: blocking IRS readout for order ms)
                                                      - trigger readout is limited to 2Hz for some as-yet-unknown reason (CAUSE: threading issue in ARAAcqd)
                                                      - low 'first block' in event data (CAUSE: transitions in signals)
                                                      - odd fluctations around block 20 in event data (CAUSE: pick up from too many simultaneous transitions)
                                                      STILL OPEN:
                                                      - addition of a 'reset' method to firmware for clean start up of FPGA+FX2
                                                      - test updated FX2 firmware from Jonathan - second update to be tested
                                                      - started integration and testing of surface trigger: v0 card will probably not meet our needs, v1 card to arrive this week from Uwe; combinatoric signal not seen in Chipscope
          - ICRR status
            . SBC ............................... ARA2 operating system runs, was able to load the FPGA on the ICRR, and was able to read board id and version registers
            . ICRR board ..................... trigger: checked the diode trigger inputs (all good, see clean, +225 mV signals from VAM-6 for SNR ~10 input signals)
                                                                 awaiting 220 uH inductors to power the batwing trigger inputs that are now being configured to be diode triggers
                                                      signal: checked all rf signal inputs - all but one are good: discone rf signal input 3 has a bad rf transformer; components ordered, to arrive Monday
                                                      FPGA: need to switch batwing (+/-) trigger to discone (+) only triggers
                                                                 need to fix the SMB trigger so that it reads out the proper time window when there's a trigger and does not break the rf trigger time window
                                                                 need to replace trigger algorithm with 3/8 (5/16?) from either batwing or discone inputs
            . calpulser interface ........... talking with Ryan, Jonathan, and Patrick about a USB<->I2C (3.3V) converter
          - ARAAcqd ......................... update needed for proper surface trigger threshold scan 
          - calibration data-taking ........ Vadj scan done, but other data will not be collected before DAQ assembly due to ATRI board death

     E - calibration pulser

          - control board .................... received boards back from Patrick, need to test new pulser
          - deep board ....................... instructions for testing from Kara, need to finish power box & DAQ box and then test

     F - cables (Travis/Ben/Windell)

          - LMR-610 .......................... ELOG done with S12 & TDR measurements (shipped to Pole)
          - 6m Helix .......................... S12 & TDR measurements done, data needs to put on ELOG (shipped to Pole)
          - downhole fiber .................. S12 & Power measurements done - one poor fiber, all else okay

     G - surface antenna integration (Peter/Travis/Brendan/Luca)

. Preamps ..................................... tested warm (noise meter & network analyzer; setting filter window) - will need to be lock-tighted, etc. later
. Receiver box ............................... tested warm (with pulser pulser)
. Power detectors .......................... tested; redoing wiring (switch to Teflon/twist pairs) as prep for placement in DAQ box
. V0 Surface TDA .......................... can set DACs; card is probably not useable: threshold to close to edge of card; also surface combinatoric trigger signal not seen with pulser so firmware needs a fix
. V1 Surface TDA .......................... to arrive this week from Uwe?

     H - antennae (Peter/Christian/Brian)
     I - shipping

3 - ANITA3 hardware development (main meeting: moved to Wednesdays)

     A - Firmware Update (Lisa)
          1. Xilinx eval board Implementation check status? (w/Luca)
     B - ASICs updates (Gary)
          1. LAB4 are in hand (eval board - Gary start - Zhe finish?)
          2. RITC are in hand (eval board - Kurtis start - Zhe finish?)
          3. ARM silicon compilation check IBM 130nm (Lisa/Luca)
    C - SURF/TURF plans (Zhe Cao arrived)

4 - EVA placeholder

5 - All other business

31-OCT-2011 3:00pm (local Radio meeting):

This Halloween, we return to our meeting to its normal time and place, 3PM in Gary's Lab ... if anyone
wants to call in, the phone number is:

                                                        (808) 956-2920

Agenda:

I note, though, that this phone is only one line, so it's availability is first come/first served.  That said,
the agenda is:

1 - AMBER (Rishi in Argentina)   Roberto's presentation  [PDF]

2 - ARA  [n.b.: the deployment dates have moved back by 1-ish weeks]

     A - building the various enclosures (Christian/Brian)

          - pre-amps ........................... done
          - downhole optical zonus ....... finished ... off to iriditing; estimated return: Friday or Monday
          - receiver boxes ................... done
          - power box ......................... done
          - DAQ box ........................... done

     B - testing the pieces in the Freezer (Brendan/Ben)

          - LARK notched filters ......... 21 tested and good
          - LARK not-notched filters ... 19 (maybe 20) tested
          - optical zonus ................... 15 good cold tested, 1 warm tested good, 1 of 16 good ones found bad when retested on Sunday
          - ATRI board ...................... 

     C - assembly (Travis)

          - pre-amps ........................ assembled, tested warm, 17 tested cold ... switched out 2 LARK filters to improve noise curve; need to see if rejects ones within specs
          - downhole optical zonus ....
          - receivers (FOAM) ............ parts in; 4 box ready & warm tested with network analyzer, awaiting gaskets to complete task (Travis/Brian)
          - power box ....................... 15V supply in place, use 12 ferrites per line, plan for laying out wiring done; aim: get it done today/tomorrow (Windell/Brendan)
          - DAQ box ......................... plan for supports for Moxa, deep antenna input chain, and Rb clock to be made Monday; aim: get it done this week (Brian/Brendan/Luca)
          - power->DAQ box cable ..... one cable ready, second one deferred to work on DAQ box assembly (Brian)

     D - DAQ system (Brendan/Ben/Luca)

          - DDA_EVAL ....................... working: can read/write to DDA & read out a pedestal trigger from DDA
          - DDA status ....................... need to replace WF2 connectors with WF connects; need to clean Samtec connectors; need to return bad LS bit DDA' to Patrick 
          - TDA status ....................... all four channels work; see expected gain
                                                     TO DO: - need to replace power overload sense resistors
                                                                 - have threshold curves for 3 out of 4 TDAs using 5 dB attenuators; need to do threshold curves for 1 TDAs; need to decide upon input attenuation
          - surface TDA status ........... ARAacqd software now able to control DAC & do threshold scans
          - temperature board ............. received from Patrick, will tested after being integrated into DAQ box
          - ATRI status/firmware
            . SBC ............................... OSU one crashes rather often too
                                                      locks up rather more often than not, usually during a read to the flash card
            . FPGA ............................. continuing to debug the event readout
                                                      - self-triggered data exhibits one time-bin spikes and dips when trigger rate rises above ~2 to 20 Hz (CAUSE: blocking IRS readout for order ms)
                                                      - trigger readout is limited to 2Hz for some as-yet-unknown reason (CAUSE: threading issue in ARAAcqd)
                                                      - low 'first block' in event data (CAUSE: transitions in signals)
                                                      - odd fluctations around block 20 in event data (CAUSE: pick up from too many simultaneous transitions)
                                                      STILL OPEN:
                                                      - addition of a 'reset' method to firmware for clean start up of FPGA+FX2
                                                      - test updated FX2 firmware from Jonathan - second update to be tested
                                                      - started integration and testing of surface trigger: v0 card will probably not meet our needs, v1 card to arrive this week from Uwe; combinatoric signal not seen in Chipscope
                                                      NEW PROBLEM:
                                                      - FX2 (Cypress) chip died; reason somewhat unknown; replacement ATRI boards coming from Patrick; purchased replacement FX2 chips
          - ARAAcqd ......................... update needed for proper surface trigger threshold scan 
          - calibration data-taking ........ Vadj scan done, but other data will not be collected before DAQ assembly due to ATRI board death

     E - calibration pulser

          - control board .................... received boards back from Patrick, need to test new pulser
          - discuss Kara's presentation

     F - cables (Travis/Ben/Windell)

          - LMR-610 .......................... ELOG done with S12 & TDR measurements (shipped to Pole)
          - 6m Helix .......................... S12 & TDR measurements done, data needs to put on ELOG (shipped to Pole)
          - downhole fiber .................. S12 & Power measurements done - one poor fiber, all else okay

     G - surface antenna integration (Peter/Travis/Brendan/Luca)

. Preamps ..................................... tested warm (noise meter & network analyzer; setting filter window) - will need to be lock-tighted, etc. later
. Receiver box ............................... tested warm (with pulser pulser)
. Power detectors .......................... tested; redoing wiring (switch to Teflon/twist pairs) as prep for placement in DAQ box
. V0 Surface TDA .......................... can set DACs; card is probably not useable: threshold to close to edge of card; also surface combinatoric trigger signal not seen with pulser so firmware needs a fix
. V1 Surface TDA .......................... to arrive this week from Uwe

     H - antennae (Peter/Christian/Brian)
     I - shipping
3 - ANITA3 hardware development (main meeting: moved to Wednesdays)
     A - Firmware Update (Lisa)
          1. Xilinx eval board Implementation check update -- Wednesday presentation (w/Luca)
     B - ASICs updates (Gary)
          1. LAB4 are in hand (eval board - Gary start, Zhe finish?)
          2. RITC are in hand (eval board - Kurtis start, Zhe finish?)
          3. ARM silicon compilation check IBM 130nm (Lisa/Luca)
    C - SURF/TURF plans (Zhe Cao here!)

4 - EVA placeholder

5 - All other business

24-OCT-2011 11:00am (note unusual time):


Agenda:
1 - AMBER (Rishi/Roberto/Peter)   [pdf]

2 - ARA

     A - building the various enclosures (Christian/Brian)

          - pre-amps ........................... done
          - downhole optical zonus ....... finished ... off to iriditing?
          - receiver boxes ................... done
          - power box ......................... done
          - DAQ box ........................... done

     B - testing the pieces in the Freezer (Brendan/Ben)

          - LARK notched filters ......... 21 tested and good
          - LARK not-notched filters ... 16 tested, more tested over last week, not sure how many are left
          - optical zonus ................... 15 good cold tested, 1 warm tested good, 1 of 16 good ones found bad when retested on Sunday
          - ATRI board ...................... 

     C - assembly (Travis)

          - pre-amps ........................ assembled, tested warm, 17 tested cold ... switched out 2 LARK filters to improve noise curve; need to see if rejects ones within specs
          - downhole optical zonus ....
          - receivers (FOAM) ............ parts in; one box ready & warm tested, aim: get it done this week (Travis/Brian)
          - power box ....................... ready for assembly, power budget done, aim: get it done this week (Windell/Brendan)
          - DAQ box .........................
          - power->DAQ box cable .... Peter needs to talk with Brian about how to make this cable properly

     D - DAQ system (Brendan/Ben/Luca)

          - DDA_EVAL ....................... working: can read/write to DDA & read out a pedestal trigger from DDA
          - DDA status ....................... need to replace WF2 connectors with WF connects; need to fix bad LS bit on DDA in daughter slot 4 (will replace with new DDA from Patrick)
          - TDA status ....................... all four channels work; see expected gain
                                                     TO DO: - need to replace power overload sense resistors
                                                                 - need to do threshold curves for all TDAs and match attenuators if need be
          - surface TDA status ........... ARAacqd software now able to control DAC
          - ATRI status/firmware
            . SBC ............................... OSU one crashes rather often too
                                                      locks up rather more often than not, usually during a read to the flash card
            . FPGA ............................. continuing to debug the event readout
                                                      - self-triggered data exhibits one time-bin spikes and dips when trigger rate rises above ~2 to 20 Hz (CAUSE: blocking IRS readout for order ms)
                                                      - trigger readout is limited to 2Hz for some as-yet-unknown reason (CAUSE: threading issue in ARAAcqd)
                                                      - low 'first block' in event data (CAUSE: transitions in signals)
                                                      - odd fluctations around block 20 in event data (CAUSE: pick up from too many simultaneous transitions)
                                                      STILL OPEN:
                                                      - addition of a 'reset' method to firmware for clean start up of FPGA+FX2
                                                      - test updated FX2 firmware from Jonathan - second update to be tested
                                                      - started integration and testing of surface trigger
          - ARAAcqd ......................... update needed for surface trigger threshold scan
          - calibration data-taking ........ 

     E - calibration pulser

          - control board .................... received boards back from Patrick, need to test new pulser

     F - cables (Travis/Ben/Windell)

          - LMR-610 .......................... ELOG done with S12 & TDR measurements (shipped to Pole)
          - 6m Helix .......................... S12 & TDR measurements done, data needs to put on ELOG (shipped to Pole)
          - downhole fiber .................. S12 & Power measurements done - one poor fiber, all else okay

     G - surface antenna integration (Peter/Travis/Brendan/Luca)

. Preamps ..................................... warm testing (noise meter & network analyzer; setting filter window) - will need to be lock-tighted, etc. later
. Receiver box ............................... ready for testing
. Power detectors .......................... ready for testing
. V0 Surface TDA .......................... can set DACs; started to look singles from it via ChipScope; initial results look problematic

     H - antennae (Peter/Christian/Brian)
     I - shipping
3 - ANITA3 hardware development (main meeting: moved to Wednesday)
     A - Firmware Update (Lisa)
          1. Xilinx eval board Implementation check status? (w/Luca)
     B - ASICs updates (Gary)
          1. LAB4 are in hand (eval board - Gary start)
          2. RITC are in hand (eval board - Kurtis start)
          3. Good news from PSEC4 (same process as RITC)
          4. ARM silicon compilation check IBM 130nm (Lisa/Luca)
    C - SURF/TURF plans (Zhe Cao arrives Friday Oct. 28)  [Gary away 10/27 - 10/30]
4 - EVA placeholder

5 - All other business

10-OCT-2011 3:00pm (local Radio meeting):


Agenda:
1 - AMBER (Rishi/Roberto/Peter)

2 - ARA

     A - building the various enclosures (Christian/Brian)

          - pre-amps ........................... done
          - downhole optical zonus ....... finishing machining the small parts - aiming to be done today/tomorrow, then off to iriditing
          - receiver boxes ................... done
          - power box ......................... done
          - DAQ box ........................... done

     B - testing the pieces in the Freezer (Brendan/Ben)

          - LARK notched filters ......... 21 tested and good
          - LARK not-notched filters ... 16 tested, 5 more to be tested
          - optical zonus ................... 15 good cold tested, 1 warm tested good
          - ATRI board ...................... 

     C - power board (Windell)

          - boards populated and tested, freezer tested okay

     D - assembly (Travis)

          - pre-amps ........................ assembled, tested warm, 17 tested cold [png] ... switched out 2 LARK filters to improve noise curve; need to see if rejects ones within specs
          - downhole optical zonus
          - receivers (FOAM) ............ will start assembling this week with available gasket; standoffs needed to complete assembly should arrive today
          - power box ....................... assembled box w/o gaskets and now testing RFI seal; awaiting rf gaskets
          - DAQ box

     E - DAQ system (Brendan/Ben/Luca)

          - DDA_EVAL ....................... working: can read/write to DDA & read out a pedestal trigger from DDA
          - DDA status ....................... need to replace WF2 connectors with WF connects; need to fix bad LS bit on DDA in daughter slot 4
          - TDA status ....................... all four channels work; see expected gain
                                                     TO DO: - need to replace power overload sense resistors
                                                                 - need to do threshold curves for all TDAs and match attenuators if need be
          - surface TDA status ........... ARAacqd software now able to control DAC
          - ATRI status/firmware
            . SBC ............................... OSU one crashes rather often too
                                                      locks up rather more often than not, usually during a read to the flash card
            . FPGA ............................. continuing to debug the event readout
                                                      - self-triggered data exhibits one time-bin spikes and deeps when trigger rate rises above between 2 and 20 Hz (CAUSE: blocking IRS readout for order ms)
                                                      - trigger readout is limited to 2Hz for some as-yet-unknown reason (CAUSE: threading issue in ARAAcqd)
                                                      - low 'first block' in event data (CAUSE: transitions in signals)
                                                      - odd fluctations around block 20 in event data (CAUSE: pick up from too many simultaneous transitions)
                                                      STILL OPEN:
                                                      - addition of a 'reset' method to firmware for clean start up of FPGA+FX2
                                                      - firmware integration for surface trigge

     F - calibration pulser

          - control board .................... test through RS-232 okay; sent boards to Patrick for testing/integration with ATRI+SBC

     G - cables (Travis/Ben)

          - LMR-610 .......................... ELOG done with S12 & TDR measurements

     H - surface antenna integration (Peter/Travis/Brendan/Luca)

. Preamps ..................................... warm testing (noise meter & network analyzer; setting filter window) - will need to be lock-tighted, etc. later
. Receiver box ............................... ready for testing
. Power detectors .......................... ready for testing
. V0 Surface TDA .......................... can set DACs; need to do test with ATRI to see if it is too noisy

     I - antennae (Peter/Christian/Brian)

     J - shipping (Oct 12th deadline for Dec 10th OnIce date)

         - cables, tools, etc.
3 - ANITA3 hardware development (main meeting: moved to ?)
     A - Firmware Update (Lisa)
          1. Xilinx eval board Implementation check status? (w/Luca)
     B - ASICs updates (Gary)
          1. LAB4 are in hand (eval board - Gary start)
          2. RITC are in hand (eval board - Kurtis start)
          3. Good news from PSEC4 (same process as RITC)
          4. ARM silicon compilation check IBM 130nm (Lisa/Luca)
    C - SURF/TURF plans (Zhe Cao circa Oct. 15)
4 - EVA placeholder

5 - All other business

3-OCT-2011 3:00pm (local Radio meeting):

No Wednesday ARA HW meeting -- action locus in Hawaii. 

Agenda:
1 - AMBER (Rishi/Roberto/Peter)

     . as appropriate, summary of the morning telephone meeting 

2 - ARA

     A - building the various enclosures (Christian/Brian)

          - pre-amps ........................... done
          - downhole optical zonus ....... being machined - aiming to be done this week; then iriditing
          - receiver boxes ................... done
          - power box ......................... done
          - DAQ box ........................... done

     B - testing the pieces in the Freezer (Brendan/Ben)

          - LARK notched filters ......... 21 tested and good
          - LARK not-notched filters ... 16 tested, 5 more to be tested
          - optical zonus ................... 15 good cold tested, 1 warm tested good
          - ATRI board ...................... 

     C - power board (Windell)

          - boards populated and tested, freezer tested okay

     D - assembly (Travis)

          - pre-amps ........................ assembled, tested warm, 16 tested cold ... switched out 2 LARK filters to improve noise curve; need to see if rejects ones within specs
          - downhole optical zonus
          - receivers (FOAM) ............ will start assembling this week with available gasket; standoffs needed to complete assembly should arrive today/tomorrow
          - power box ....................... awaiting rf gaskets
          - DAQ box

     E - DAQ system (Brendan/Ben/Luca/Mike D.)

          - DDA_EVAL ....................... working: can read/write to DDA & read out a pedestal trigger from DDA
          - DDA status ....................... need to replace WF2 connectors with WF connects; need to fix bad LS bit on DDA in daughter slot 4
          - TDA status ....................... all four channels work; see expected gain
                                                     TO DO: - need to replace power overload sense resistors
                                                                 - need to do threshold curves for all TDAs and match attenuators if need be
          - surface TDA status ........... ARAacqd software now able to control DAC
          - ATRI status/firmware
            . SBC ............................... OSU one crashes rather often too
                                                      locks up rather more often than not, usually during a read to the flash card
            . FPGA ............................. continuing to debug the event readout
                                                      SOLVED:
                                                      - self-triggered data exhibits one time-bin spikes and deeps when trigger rate rises above between 2 and 20 Hz
                                                      - trigger readout is limited to 2Hz for some as-yet-unknown reason
                                                      STILL OPEN:
                                                      - soft triggered event data has a low 'first block' event data
                                                      - addition of a 'reset' method to firmware for clean start up of FPGA+FX2
                                                      - firmware integration for surface trigger

          - shipping to Patrick: old ATRI boards, spare new ATRI boards, NTU SBC, ARA3 SBC, set of 4 TDA & DDAs (Peter)

     F - calibration pulser

          - control board .................... test through RS-232 okay; sent boards to Patrick for testing/integration with ATRI+SBC

     G - cables (Travis/Ben)

          - LMR-610 .......................... ELOG done with S12 & TDR measurements

     H - surface antenna integration (Peter/Travis/Brendan)

. Preamps ..................................... warm testing (noise meter & network analyzer; setting filter window) - will need to be lock-tighted, etc. later
. Receiver box ............................... ready for testing
. Power detectors .......................... ready for testing
. V0 Surface TDA .......................... can set DACs; need to do test with ATRI to see if it is too noisy

     I - antennae (Peter/Christian/Brian)

     J - shipping (Oct 6th deadline?)

         - cables, tools, etc.
3 - ANITA3 hardware development (main meeting: Thursday @ 11AM)
     A - Firmware Update (Lisa)
          1. Xilinx eval board Implementation check status?? (w/Luca)
     B - ASICs updates (Gary)
          1. LAB4 are in hand (eval board - Gary start)
          2. RITC are in hand (eval board - Kurtis start)
          3. Good news from PSEC4 (same process as RITC)
          4. ARM silicon compilation check IBM 130nm (Lisa/Luca)
    C - SURF/TURF plans (Zhe Cao circa Oct. 15)

4 - EVA placeholder

5 - All other business

12-SEP-2011 3:00pm (local Radio meeting):

No Wednesday meeting -- action locus in Hawaii.  Ryan's arrival below incorrect (9/8); Mike dates?

Agenda:
1 - AMBER (Rishi/Roberto)

2 - ARA

     A - building the various enclosures (Christian/Brian)

          - pre-amps ............. done
          - optical zonus ....... design approved; machining to begin this week .... will take o(2 weeks)
          - receiver boxes ..... machining fiber support, probably ready for assembly this week
          - power box ........... out for iriditing today/tomorrow after quote received ... return end of next week
          - DAQ box ............  out for iriditing today/tomorrow after quote received ... return end of next week

     B - testing the pieces in the Freezer (Brendan/Ben)

          - LARK notched filters ........ 21 tested and good
          - LARK not-notched filters ... 16 tested, 5 more to be tested
          - optical zonus ................... 15 good, 1 remaining to test ... have accounted for all sets of RX/TXs
          - ATRI board ...................... in the freezer last Monday w/2 DDAs & 1 TDA; okay results

     C - power board (Windell/Brendan)

          - boards populated and tested; replace wires with teflon wires?; freezer test this week hopefully

     D - assembly (Travis)

          - pre-amps ........................ 13 assembled, rest awaiting screws - 4 in freezer
          - optical zonus
          - receivers
          - power box
          - DAQ box

     E - DAQ system (Patrick/Ryan/Luca/Brendan/Ben)

         - TDA status ....................... all four TDAs at UH; one needs mod for current limit
         - DDA status ....................... all four DDAs at UH
         - ATRI status/firmware
           . ATRI board ..................... new ATRI board; connections tested; read pedestal data all there and looks better
           . SBC ............................... OSU SBC is happy; UH on still locks up - going to try old kernel to match OSU system
           . FPGA/DAQ ..................... pedestal runs doable; event readout tested modulo fixing any new bugs, simple trigger ready

           What's next?

     F - calibration pulser (Peter/Patrick/Gary)

          - Ru clock ........................... tested one at UH; return to Accubeat for square wave modification
          - rf pulse generator ... Design review of modified board (4pm) for submission
          - control system

     G - surface antenna integration (Uwe/Peter - circa Sunday evening)
 
     Components
			Boxes				ordered, but not yet delivered
			Cable				at UH
			LNAs				ordered, but not yet delivered, alternative available
			Filters				at UH
			Notches				at UH
			Splitter			at UH
			Bias-Ts				at UH
			PowerDetectors			at UH
			Connectors			at UH
			FlightCommNotches		at UH, but with F-Connectors, Att @ 125 MHz only 20 dB

     Assembling 		
			ReceiverBox 			Ready
			SplitterPad			Ready	
			Frontend			waiting for boxes, when available, estimated 2 days for mounting components
			testing				after mounting, estimated 1/2 day

     SurfaceAntennasTriggerBoard
			Revision 0 			at UH, Samtecs soldered, ready for testing
			Revision 1			Boards needs same preparation because of partially wrong solder mask
			(modified TDA) 			Done on Sep/12, Component soldering starting Sep/12
			              			additional needed Parts ordered, expected to be at UH on Sep/15

     Firmware
			FPGA Configuration		Ready and Tested on a Xilinx Evalboard with board rev 0
G - Review presentation (this Thursday or next Thursday?)
3 - ANITA3 hardware development (main meeting: Thursday @ 11AM)
     A - Firmware Update (Lisa)
          1. Xilinx eval board Implementation check status?? (w/Luca)
     B - ASICs updates (Gary)
          1. RITC back Aug. 19 --> early Sept?? (mid Sept packaged?)
          2. LAB4 are in hand (eval board - Gary start)
          3. RITC evaluation board (Kurtis)
          4. ARM licensing, silicon compilation check IBM 130nm (Luca)
    C - SURF/TURF plans (Zhe Cao circa Oct. 15)

4 - EVA placeholder (kick-off meeting after ARA madness??)

5 - All other business

6-SEP-2011 3:00pm (local Radio meeting):

No Wednesday meeting -- action locus in Hawaii.  Mike dates?

Agenda:
1 - AMBER (Rishi/Roberto) 
        - Calibration update  [PDF]

2 - ARA

     A - building the various enclosures (Christian/Brian)

          - pre-amps ............. done
          - optical zonus ....... still being designed
          - receiver boxes ..... redesigned w/o filter pins, probably ready for assembly this week
          - power box ............ ready to be sent for iriditing
          - DAQ box ............. ready to be sent for iriding?

     B - testing the pieces in the Freezer (Brendan/Ben)

          - LARK notched filters ........ 21 tested and good
          - LARK not-notched filters ... 16 tested, 5 more to be tested
          - optical zonus ................... 15 good, 1 remaining to test ... have accounted for all but one set of RX/TXs
          - ATRI board ...................... in the freezer on Monday w/2 DDAs & 1 TDA

     C - power board (Windell)

          - boards populated and tested, freezer test this week with 300V power supply arrives (which works at least up to 50V)

     D - assembly (Travis)

          - pre-amps ........................ bias-tee <-> amp done, 2 assemblies done, more done by the end of the day
          - optical zonus
          - receivers
          - power box
          - DAQ box

     E - DAQ system (Brendan/Ben/Luca/Jonathan) ... Patrick & Ryan arrive today or tomorrow

         - DDA_EVAL ....................... working: can read/write to TDA & read out a pedestal trigger from DDA
         - TDA status ....................... all four channels work; see expected gain
         - ATRI status/firmware
           . SBC ............................... threshold scans done, event readout done
                                                     locks up rather more often than not, usually during a read to the flash card
           . FPGA ............................. can synthesize and load FPGA via JTAG and SBC, communicate with I2C devices, scalers work, thresholds work, readout data
                                                     - event data has OE-striping problem with stack 1 and one of the DDAs is 'bad'
                                                     - working on integrating Thomas's IRS readout code with firmware; 1st trigger available from Luca

     F - cables (Travis/Ben)

          - LMR-610 .......................... ELOG done with S12 & TDR measurements

     G - surface antenna integration (Uwe/Peter ... circa Thursday 9/1 morning, i.e., not quite up-to-date)

Components
- Boxes ordered, but not yet delivered
- Cables at UH
- LNAs ordered, but not yet delivered; alternatives available at UH
- Filters at UH
- Notches at UH
- Splitter at UH
- Bias-Ts at UH
- PowerDetectors at UH
- Connectors at UH
Assembly 
			           - mounting                                       waiting for boxes , when available, estimated 2 days for mountimg components
			           - testing                                           after mounting, estimated 1 day
			
             SurfaceAntennasTriggerBoard
			           - Revision 0                                     at UH, but no samtec-connectors soldered, estimated Sept/02
			           - Revision 1		
			           - based on the InIceTriggerboard
			           - (modified TDA)                              Layout sent to 4pcb for production, estimated delivery Sept/6/2011
								                          additional Parts ordered, estimated delivery Sept/5/2011
             Firmware
			           - FPGA Configuration 	                  Ready and Tested on a Xilinx Evalboard with board rev 0
     H - Testbed Reboot On Thursday (Brendan)

      I -  IRS3  (Gary)
            1. Layout asymmetry and sample bus loading
            2. Improved layout for Wilkinson registers, output bus
            3. Read address counter --> increase power/gnd pins at chip right side

3 - ANITA3 hardware development (main meeting: Thursday @ 11AM)

     A - Firmware Update (Lisa)
     B - ASICs updates (Gary)
          1. RITC back Aug. 19 --> early Sept?? (mid Sept packaged?)
          2. LAB4 are in hand (eval board - Gary start)
          3. RITC evaluation board (Kurtis)
    C - SURF/TURF plans (Zhe Cao circa Oct. 15)

4 - EVA
  1. When does money turn on?
  2. Timescale?
5 - All other business

31-AUG-2011  Meeting:

Agenda:
  1. Follow-up action items from Taiwan review:
    1. Status of BOM/parts procurement, additional ATRI
    2. Tracking database for subcomponents, fabricated components, testing status/disposition    -- any progress?
  2. Institutional updates:
    1. OSU update  [PDF?]
    2. NTU update: [PDF?]
    3. UCL update:   [PDF?]
    4. Brussels update:    [PDF?]
    5. Hawaii:     [PDF?]
  3. Hawaii integration party:
  4. AOB? 

29-AUG-2011 3:00pm (local Radio meeting):

1 - AMBER (Rishi/Roberto)

2 - ARA

     A - building the various enclosures (Christian/Brian)

          - pre-amps ............. back from iriditing?
          - optical zonus ....... still being designed
          - receiver boxes ..... redesigned w/o filter pins, probably ready this week
          - power box ............ probably done - will need to iridited
          - DAQ box ............. being designed - issues: calibration controller plans

     B - testing the pieces in the Freezer (Brendan/Ben)

          - LARK notched filters ........ 21 tested and good
          - LARK not-notched filters ... discovered that they pass >2 GHz, still have 11 more to test this week
          - optical zonus ................... results from first 4, maybe first 8?

     C - power board (Windell)

          - boards populated and being tested, freezer test this week when 300V power supply arrives

     D - assembly (Travis)

          - pre-amps ............ bias-tee <-> amp done, screws here?
          - optical zonus
          - receivers
          - power box
          - DAQ box

     E - DAQ system (Brendan/Ben/Luca/Jonathan)

         - DDA_EVAL ....................... working: can read/write to TDA & read out a pedestal trigger from DDA
         - TDA status ....................... all four channels work; see expected gain
         - ATRI status/firmware
           . SBC ............................... USB<->FPGA issue resolved, threshold scans done, event readout maybe possible
                                                     locks up once or twice a day?
           . FPGA ............................. can synthesize and load FPGA via JTAG and SBC, communicate with I2C devices, scalers work, thresholds work

     F - cables (Travis/Ben)

     G - surface antenna integration (Uwe/Peter)

3 - ANITA3 hardware development (main meeting: Thursday @ 11AM)

     A - Firmware Update (Lisa)
     B - ASICs updates (Gary)
          1. RITC back Aug. 19 (early Sept packaged?)
          2. LAB4 are in hand
          3. Plan for an evaluation board?
    C - SURF/TURF plans (Zhe Cao circa Oct. 15)

4 - Any other business

24-AUG-2011  Meeting:

Agenda:
  1. Follow-up action items from Taiwan review:
    1. Status of BOM/parts procurement, additional ATRI
    2. Tracking database for subcomponents, fabricated components, testing status/disposition    -- any progress?
  2. Institutional updates:
    1. OSU update  [PDF]
    2. NTU update: [PDF?]
    3. UCL update:  
    4. Brussels update:
    5. Hawaii -- DDA/TDA [txt info] [docDB link] testing and debug
  3. AOB? 

22-AUG-2011 3:00pm (local Radio meeting):

  1. AMBER status
  2. ARA construction
    1. Building the various enclosures  (Christian/Brian)
    2. Testing the pieces in the Freezer (Brendan/Ben)
    3. Power Board (Windell)
    4. Assembly (Travis)
    5. DAQ system (Brendan/Ben)
  3. ANITA3 hardware development  [Thursday @ 11am]
    1. Firmware update (Lisa)
    2. ASICs updates (Gary)
      1. RITC back Aug. 19 (early Sept packaged?)
      2. LAB4 here!
      3. Plans for eval boards?
    3. SURF/TURF plans -- ~Oct. 15  (Zhe Cao)
  4. AOB

8-AUG-2011  Phone Meeting: only 30' -- a number of follow-up e-mail discussions

Documents (10-AUG-2011//JST):
  1. Firmware (ULB) for trigger handling  [PDF]
  2. ATRI Register definitions (Patrick)  [PDF]


Agenda:
  1. Follow-up action items from Taiwan review:
    1. BOM/parts procurement for additional ATRI
      1. FPGAs?  -- arrived?
      2. BOM?  -- shipped?
    2. Patrick: quotation for additional ATRI assembly to NTU?
    3. Tracking database for subcomponents, fabricated components, testing status/disposition    -- any progress?
  2. Institutional updates:
    1. OSU update  [txt]
    2. NTU update:
    3. UCL update: 
    4. Brussels update:
    5. Hawaii
  3. Confirm next meeting time -- after ICRC?
  4. AOB? 

1-AUG-2011 3:00pm (local Radio meeting):

  1. AMBER status
  2. ARA construction
    1. Building the various enclosures  (Christian/Brian)
    2. Testing the pieces in the Freezer (Brendan/Ben)
    3. Power Board (Windell)
    4. DAQ system (Brendan/Ben)
  3. ANITA3 hardware development  [Thursday @ 11am]
    1. Firmware update (Lisa)
    2. ASICs updates (Gary)
      1. RITC back Aug. 9 (Aug. 20)
      2. LAB4 back Aug. 23
      3. Plans for eval boards?
    3. SURF/TURF plans -- ~Oct. 15  (Zhe Cao)
  4. AOB

27-JUL-2011  Meeting: electronic updates only


Agenda:
  1. Follow-up action items from Taiwan review:
    1. BOM/parts procurement for additional ATRI
      1. FPGAs?  -- arrived?
      2. BOM?  -- shipped?
    2. Patrick: quotation for additional ATRI assembly to NTU?
    3. Tracking database for subcomponents, fabricated components, testing status/disposition    -- any progress?
  2. Institutional updates:
    1. OSU update  [PDF?]
    2. NTU update:  [PDF] 
    3. UCL update:   [link to PDF]
    4. Brussels update:
    5. Hawaii -- DDA/TDA [txt info] [docDB link] testing and debug
  3. Confirm next meeting time 
  4. AOB? 

20-JUL-2011 Meeting: via Skype

Wednesday 05:00 Hawaii  -- Gary will attend
Wednesday 08:00 California
Wednesday 10:00 Madison
Wednesday 11:00 OSU
Wednesday 16:00 London
Wednesday 17:00 Brussels
Wednesday 23:00 Taipei

Agenda: 
  1. Follow-up action items from Taiwan review:
    1. BOM/parts procurement for additional ATRI
      1. Si5367 received?  -- yes!
      2. FPGAs ordered?  -- yes, but 6 week lead time (too long).  Subsequent follow up:  Wisconsin (Mike D) ordered 8x right away
      3. BOM -- updated delivery time? -- Digikey order to be received Thursday.  Ship out to Patrick on Friday
      4. Innodisk memory follow-up?  -- Pisin hadn't relayed discussion from with Peter; to be followed up
    2. Patrick: quotation for additional ATRI assembly to NTU?  -- supposed to receive quote "today" (salesman out ill) --> to NTU
    3. Tracking database for subcomponents, fabricated components, testing status/disposition -- needs action:  GPS debacle as exhibit A of this!!!
    4. How many additional DDA Rev. C/TDA Rev. A to build?  8x Rev. C DDA built, 2 to debug; 1x TDA to Hawaii today
    5. How to best coordinate our [very time limited] development efforts? -- these meetings??
    6. Integration party dates?  
      1. Strawman schedule  [PDF]
      2. A more official, Gantt schedule  [PDF]  a review of which lead to the following questions:
        1. How soon TDA to UH?  (Peter ready to jump on testing -- modulo jury duty) -- by end of week?
        2. GPS status?  Both NTU (3x systems) and Chiba providing?  -- NTU will cold test one set, send spare set to Hawaii
        3. More TTL boost?  Adopt CMOS option per Patrick?  -- no discrete (Compac able) board; Hawaii should design if needed
  2. Institutional updates:
    1. OSU update  -- board fab madness;  progressing, waiting on parts.  Possible Ryan visit, though need to coordinate around ICRC (Aug 11 - 18)
    2. NTU update   -- software trigger working, event flow debug still needed.  Down-hole testing in Hawaii:  perhaps start immediately after ICRC == to be discussed with Pisin
    3. UCL update   -- Cypress FX2 poking, remote debug inefficient.  Higher level software "there".  ATRI access limitations (boards needed, as per above)
    4. Brussels update  -- Kael en route Madison.  dda_eval_event_FIFO modules complete.  Thomas working on documentation.  Kael to bring board back from Madison.  Various cold and network testing there proposed.  Discussion needed?  (next week?)
    5. Hawaii  -- hardware repair on DDA Rev. B (IRS2 soldering).  Power system progressing.  Discussion on schedule.  1 Rev. C DDA/1 TDA to be shipped for immediate testing "today?"
  3. Next meeting time? --> delayed by 1 hour proposed  (Gary @ PANIC in Boston) 
  4. AOB? 

18-JUL-2011 2:30pm (local Radio meeting):

  1. AMBER status
    1. 2x pathologies?  [1 is event formatting; 1 is really HW/buffer problem?]  [PDF]
    2. Plans for a repair mission?
    3. Any physics results?
  2. ARA testbed updates 
    1. testbed update?  (Brendan)
    2. plans for further testing?
  3. ARA year 1 (2 stations) -- Gantt schedule update  [PDF]
    1. Usual "Wednesday" station development meeting (5am HST)
    2. Test plans for ATRI, DDA, TDA
    3. Schedule for station hardware integration/test; strawman  [PDF]
    4. One issue on power system:  "HV" 100uF Vicor input caps  [PDF]
  4. ANITA3 hardware development  [Thursday @ 11am]
    1. Firmware update (Lisa)
    2. ASICs updates (Gary)
      1. RITC back Aug. 9 (Aug. 20)
      2. LAB4 back Aug. 23
      3. Plans for eval boards?
    3. SURF/TURF plans -- Oct. 15(?)  (Zhe Cao)
  5. AOB

13-JUL-2011  Meeting: via Skype

Wednesday 16:00 Hawaii
Wednesday 19:00 California
Wednesday 21:00 Madison
Wednesday 22:00 OSU
Thursday    03:00 London  -- attendance not expected
Thursday    04:00 Brussels  -- attendance not expected
Thursday     10:00 Taipei

Agenda:

  1. Follow-up action items from Taiwan review:
    1. BOM/parts procurement for additional ATRI  (update)
      1. Si5367 delivery?   --shipped!  Fedex tracking number sent
      2. FPGAs?
      3. BOM?
    2. Patrick: quotation for additional ATRI assembly to NTU?
    3. Tracking database for subcomponents, fabricated components, testing status/disposition
    4. How to best coordinate our [very time limited] development efforts?
    5. Gantt chart of critical path?  (until end of July to pull trigger on moving effort to Hawaii)
  2. Institutional updates:
    1. OSU update  [PDF?]
    2. NTU update:  Adding software trigger and pedestal readout functions in NTU software/hardware.  UDP packet data study/reconstruction.  NTU software shows raw ADC counts.  Waveform display function will be added.
    3. UCL update:  Some progress USB readout software.  Debug software working tomorrow -- can be used to bootstrap fashion to debug firmware, and so forth. -- Request to confirm possible integration dates in Hawaii
    4. Brussels update
    5. Hawaii -- touch base locally (just returned)
  3. Confirm next meeting time 
  4. AOB? 

7-JUL-2011 Meeting: via Skype (if any change, will send via e-mail)

Wednesday 04:00 Hawaii  -- attendance not expected
Wednesday 07:00 California
Wednesday 09:00 Madison
Wednesday 10:00 OSU
Wednesday 15:00 London
Wednesday 16:00 Brussels
Wednesday 22:00 Taipei
Wednesday 23:00 Nagoya

Agenda: 
  1. Follow-up action items from Taiwan review:
    1. BOM/parts procurement for additional ATRI  (these are addressed in NTU update presented below)
      1. Si5367 delivery?
      2. FPGAs?
      3. BOM?
    2. Patrick: quotation for additional ATRI assembly to NTU?
    3. Tracking database for subcomponents, fabricated components, testing status/disposition
    4. How many additional DDA Rev. C/TDA Rev. A to build?
    5. How to best coordinate our [very time limited] development efforts?
    6. (do we have a schedule?  'critical path'?)
  2. Institutional updates:
    1. OSU update  [PDF]
    2. NTU update  [txt]
    3. UCL update (Jonathan on USB)  trunk description [txt]  and overview [PDF]
    4. Brussels update
    5. Hawaii -- update next week
  3. Next meeting time? 
  4. AOB? 

22-JUN-2011 4pm (OSU/10:00pm; Taipei 23-JUN 10:00am) Meeting: via Skype

Wednesday 16:00 Hawaii
Wednesday 19:00 California
Wednesday 22:00 OSU
Thursday     10:00 Taiwan.

Agenda: 
  1. Albrecht's visit, plans for next week.
  2. Institutional updates:
    1. OSU update  [PDF]
    2. NTU update  [PDF?]
    3. Hawaii -- [link] to IRS2 information (data sheet, biases)
  3. Production and procurement meeting at NTU (week of June 27)
  4. Relayed reports on status of development in Europe? (Patrick)
  5. Further discussion/plans on calibration techniques? (Kurtis)
  6. Next meeting? 
  7. AOB? 

20-JUN-2011 2:30pm (local Radio meeting):

  1. AMBER status
    1. AC issues -- all settled
    2. Anyone looking at the data?
    3. What still needed?
  2. ARA updates 
    1. testbed update?  (Brendan)
    2. Results from deathray trigger tests?
    3. status of surface trigger/antennas?  (ICRR paper?)
    4. Usual hardware development meeting Wednesday, a prelude to NTU meeting (June 27-July1)
  3. ANITA3 hardware development
    1. Firmware update (Lisa)  [PDF]
    2. ASICs submissions updates (Gary)
      1. RITC in fab queue
      2. LAB4 in fab queue? 
    3. SURF/TURF plans (Zhe Cao)
  4. AOB

Rescheduled:  3-JUN-2011 4pm (OSU/10:00pm; Taipei 4-JUN 10:00am) Meeting: via Skype

Wednesday 16:00 Hawaii
Wednesday 19:00 California
Wednesday 22:00 OSU
Thursday     10:00 Taiwan.

Agenda: 
  1. Added afterwards:  IRS2 suggested bias settings  [PDF]
  2. Institutional updates:
    1. OSU
    2. NTU -- link to existing firmware on ftp repository:  [ftp]   for which ARA/ara913 are useful.
    3. Hawaii -- status of DDA_eval assembly (Windell)
  3. Production and procurement meeting at NTU (week of June 27), Albrecht stop-over in Hawaii (June 24)
  4. Relayed reports on status of development in Europe (Patrick)
  5. Further discussion/plans on calibration techniques (Kurtis?)
  6. Next meeting? 
  7. AOB? 

31-MAY-2011 2:30pm (local Radio meeting):

  1. AMBER status
    1.  Installation report (Peter)
    2. AC issues
    3. Long-term needs?  (requests to Luca?)
  2. ARA updates 
    1. status of testbed?  (Brendan)
    2. Requests for trigger mods?
    3. status of surface trigger/antennas?  (ICRR paper?)
    4. Usual hardware development meeting tomorrow
    5. procurement/coordination meeting at NTU:  week of June 27 - July 1
  3. ANITA3 hardware development
    1. Firmware update (Lisa)
    2. ASICs submissions updates (Gary)
      1. RITC in fab queue
      2. LAB4 in fab queue
    3. SURF/TURF plans (Zhe Cao)
  4. AOB

18-MAY-2011 4pm (OSU/10:00pm; Taipei 5-MAY 10:00am) Meeting: no meeting this week due to travel

16-MAY-2011 2:30pm (local Radio meeting):

  1. AMBER plans -- further test and deployment issues/plans?
  2. ARA updates 
    1. status of testbed?
    2. status of surface trigger?
    3. Usual hardware development meeting:  no meeting this week due to travel
    4. procurement/coordination meeting at NTU:  week of June 27 - July 1
  3. ANITA3 hardware development
    1. Firmware update (Lisa)
    2. ASICs submission updates (Gary)
      1. RITC in fab queue
      2. LAB4 5/31
    3. SURF/TURF plans (Zhe Cao)
  4. AOB

11-MAY-2011 4pm (OSU/10:00pm; Taipei 5-MAY 10:00am) Meeting: via Skype

Wednesday 16:00 Hawaii
Wednesday 19:00 California
Wednesday 22:00 OSU
Thursday     10:00 Taiwan.

Agenda: 
  1. Institutional updates:
    1. OSU -- ATRI focussed:  Rev. B Overview [PDF] and comments on Clock chip [txt]
    2. NTU  [PDF]
    3. Hawaii  (status of DDA_eval assy)
  2. A review (Patrick) of the IRS block manager architecture:  [pptx]   [PDF]
  3. Nomenclature (see section 2 -- where tried to sort this out!)  from the TARGET1 paper  [PDF]
  4. Production and procurement meeting at NTU (week of June 27), Albrecht stop-over in Hawaii (June 24)
  5. Relayed report on status of development in Europe
    1. Report from Thomas Meures   [PDF]
    2. Testbench trigger  [vhd]
    3. Trigger handling  [vhd]
  6. Further discussion/plans on calibration techniques (defer -- until after RITC submission)
  7. Next meeting? 
  8. AOB? 

9-MAY-2011 3pm (local Radio meeting):

  1. AMBER plans -- further test and deployment issues/plans?
  2. ARA update 
    1. paper status -- Rev. 1 (revised) available   ARA11_arxiv_rev1  [PDF]
    2. status of testbed?
    3. status of surface trigger?
    4. strangeness in thermal noise histograms?  all:  [png]    Ch. 5:  [png]
      1. non-linearity??   LAB3 measurement  [PDF]
      2. (probably thinking of non-linearity in IRS1)   [PDF]
      3. Should be fixed in IRS2, as went back to the TARGET comparator  [PDF]    [PDF]
    5. pulse fitting results?
    6. Usual hardware development meeting:  Wednesdays at 4pm HST
    7. procurement/coordination meeting at NTU:  week of June 27 - July 1
  3. ANITA3 hardware development
    1. ASICs submission updates (Gary)
    2. SURF/TURF plans (Zhe Cao)
  4. AOB

4-MAY-2011 4pm (OSU/10:00pm; Taipei 5-MAY 10:00am) Meeting: via Skype

Agenda: 
  1. Proposed data format (Kael):  [txt]
  2. Institutional updates:
    1. OSU  [PDF]
    2. NTU  [PDF]
  3. DDA_eval Rev. B
    1. BOM  [PDF]
  4. TDA status
    1. Input chain  [PDF]
    2. Two amps, full filter suite  [PNG]
    3. Two amps, half the filters  [PNG]
    4. Amplifier  ( ABA-31563 )
      1. S21 results (very nice)  [BMP]
      2. this be the choice
  5. Production and procurement meeting at NTU (week of June 27), Albrecht stop-over in Hawaii (June 24)
  6. Report on status of development in Europe
    1. UCL software?  (Patrick about contact)  and some studies on clock alignment (Ryan/Jonathan)  [PDF]  and commentary  [txt]
    2. Belgium update (Kael)  [txt]   (he suggests keeping definitive postings on docDB.  comments?)
  7. Further discussion/plans on calibration techniques (defer -- until after May 9th) 
  8. ARA Station BOM (quick estimate -- Mike DuV)  [xlsx]
  9. AOB? 

2-MAY-2011 3pm (local Radio meeting):

  1. AMBER plans -- test and deployment schedule
  2. ARA update
    1. status of testbed?
    2. status of stuface trigger?
    3. pulse fitting results
    4. Usual hardware development meeting:  Wednesdays at 4pm HST
    5. procurement/coordination meeting at NTU:  week of June 27 - July 1
  3. ANITA3 hardware development
    1. RITC design review Thursday, May 5th at 11am in ID Lab
    2. LAB4 design review:  submit with changes 5/30 (5/2)
  4. AOB

20-APR-2011 4pm (OSU/10:00pm; Taipei 21-MAR 10:00am) Meeting: via Skype

Wednesday 16:00 Hawaii
Wednesday 19:00 California
Wednesday 22:00 OSU
Thursday     10:00 Taiwan.

Agenda: 
  1. DDA testing updates:
    1. OSU  [PDF]
    2. NTU  [PDF]
  2. ATRI status
    1. Boards received -- assy schedule?
    2. Firmware status report (13-apr-2011)  [txt]
  3. TDA Status?
  4. Further test plans at NTU?
  5. Status of development in Europe?
  6. Coordination with Belgium? 
  7. Further discussion/plans on calibration techniques?
  8. Production and procurement meeting at NTU (week of June 27)
  9. AOB? 

18-APR-2011 3pm (local Radio meeting):

  1. AMBER plans
  2. ARA update
    1. status of testbed
    2. pulse fitting results
    3. procurement/coordination meeting at NTU:  week of June 27 - July 1
  3. ANITA meeting report

6-APR-2011 4pm (OSU/10:00pm; Taipei 7-MAR 10:00am) Meeting: via Skype

Minutes:  [txt]

References for RF layout (Xilinx App Notes/User Guides) cited by Patrick:  [an530]   [ug393]

Various figures and links in 31-MAR/23-MAR meeting.

Wednesday 16:00 Hawaii
Wednesday 19:00 California
Wednesday 22:00 OSU
Thursday     10:00 Taiwan.

Links: 
  1. ARA Station 1 (year 2)  [link]
  2. Link to the ARA Wiki  [link]
  3. Repository:   svn+ssh://ara@hepts2.phys.hawaii.edu/data2/svnroot/ara  (for which usualPW/TestBed1 may be helpful)
  4. IRS testing  [link]
Agenda: 
  1. DDA testing update?
    1. OSU 
    2. NTU  [PDF]
  2. ATRI status
  3. TDA Review?
  4. Status of development in Europe?
  5. Current test plans at NTU?
  6. Status of current firmware?  What still needed?
  7. Further discussion/plans on calibration techniques?
  8. Coordination with Belgium?  (alternate meeting time?)
  9. AOB? 

30-MAR-2011 4pm (OSU/10:00pm; Taipei 31-MAR 10:00am) Meeting: via Skype

ATRI Completed design (2-APR-2011):  [link]
Minutes:  [txt]

Various figures and links in 23-MAR meeting

Agenda: 
  1. DDA testing update?
  2. ATRI status
    1. Updated schematics  [PDF]
    2. Current state of routing   [PDF]
  3. TDA Review??
  4. Status of development in Europe?
  5. AOB? 

28-MAR-2011 1:30 - 2:00pm

No agenda...

23-MAR-2011 3:30pm (OSU/9:30pm Taipei 24-MAR 9:30am) Meeting: via Skype

Minutes:  [txt]

And ATRI layout figure referenced:  [png]

Links: 
  1. ARA Station 1 (year 2)  [link]
  2. Link to the ARA Wiki  [link]
  3. Repository:   svn+ssh://ara@hepts2.phys.hawaii.edu/data2/svnroot/ara  (for which usualPW/TestBed1 may be helpful)
  4. IRS testing  [link]
Agenda: 
  1. DDA testing update?
  2. Status of OSU development?
  3. Current test plans at NTU?
  4. Status of current firmware?  What still needed?
  5. Further discussion/plans on calibration techniques?
  6. Coordination with Belgium?  (alternate meeting time?)
  7. AOB? 

22-MAR-2011 update:  [will be a meeting later in week @ 3:00pm? (ID Lab)]

  1. Action items list from Kansas (Mike D.)   [PDF]
  2. Reminder of Collaboration meeting slides: [link]    
  3. Pointer to upcoming ARA Conf presentation possibilities  [link]   (Kara)
  4. Further Trigger Thoughts from Luca (discussion?)  Posting of simulation source [tar ball]  (Peter)
  5. AOB?

18-MAR-2011 3:00pm (ID Lab)

  1. Some comments on Phase Closure (Peter)   [PDF]
  2. Timebase Calibration (from J. Davies at ARA Collab mtg [link])  [PDF]  
  3. Testbed timebase issues follow-up   [PDF]   (Brendan)
  4. AOB?

25-FEB-2011 2:30pm (ID Lab)

  1. Trigger studies update (Luca)   [PDF]
  2. For reference, talk from August Collaboration meeting on trigger (Gary)   [PDF]
  3. Studies of algorithms/simulation?  (Lisa?)
  4. Testbed timebase issues follow-up  (Brendan)
  5. AOB?

12-JAN-2011 5pm (Hawaii/11am Taipei 23-DEC) Meeting:   [link]

  1. IRS2 customs update?
  2. Further BLAB3A testing?  (essentially same as IRS2, but with amplifier)
  3. Further IRS testing at NTU
  4. Further discussion on calibration techniques
  5. AOB? 

Items raised for Year2 development

  1. RF over fiber option (Mike DuVernois)  [txt w/links]
  2. Firmware development/repository options (Patrick)  [txt]

10-JAN-2011 3:00pm?? (need to find workable time for Spring semester)

From Gary:   I will be away after next week, for a couple of weeks [someone else organize?]

0 - responses to Brendan on firmware issues?

1 - AOB?  (initial data look??)

5-JAN-2011 5pm (Hawaii/11am Taipei 6-JAN) Meeting:   [link]

  1. Meeting not held due to other works -- Chiu Chuan sent update (posted)
  2. IRS2 ASICs in Taiwan customs

22-DEC-2010 5pm (Hawaii/11am Taipei 23-DEC) Meeting:   [link]

  1. IRS2 shipment  (Jan. 3rd per webpage -- checked 12/18 GSV)
  2. Initial BLAB3A (essentially same as IRS2, but with amplifier)
  3. Further IRS testing at NTU
  4. Further discussion on calibration techniques
  5. AOB?  (e.g.  next meeting of new year?)

Items raised for Year2 development

  1. RF over fiber option (Mike DuVernois)  [txt w/links]
  2. Firmware development/repository options (Patrick)  [txt]

13-DEC-2010 1:30pm (irregular -- radio meeting) Meeting Agenda Items

From Gary:   We have a special visitor -- Roberto Mussa, for discussion on many things radio related.

0 - review Summaries/action itmes from last meeting?  (firmware TBD???)

1 - South Pole departure "last minute" items?

8-DEC-2010 5pm (Hawaii/11am Taipei 9-DEC) Meeting:   [link]

  1. Further IRS testing at NTU
  2. Further discussion on calibration techniques
  3. Update on IRS2 delivery

6-DEC-2010 1:30pm (regular) Meeting Agenda Items

From Brendan:   I think that the following tasks remain on the table with the aim of getting them done before
shipping the whole thingie:

0 - review Summary from last meeting?  (notes and slides below for reference)

1 - check if the 'PPS / Ru clock' thingie is working now that we switched the input from the
     LEMO to the SMA

2 - do the study of the Batwing trigger now that we've reduced the coincidence window by
     a factor of 2-ish to something like 50 ns and changed to the AND instead of the OR on
     negative-going and positive-going discriminators

3 - measure the noise factor for the preamp & receiver boxes at -54 C (this task does not
     need the DAQ box)

4 - update the ara1 to eliminate the sudo requirement (straight forward copy of a script from
     ara2 to ara1)

5 - clean up the ara1 disk and copy its contents to the 'backup' partition

Is there anything else that we should add to this list ... particularly any testing that we are
best served by having done prior to installing things at Pole?

From Ryan (via Gary):   Ryan says he now has a version of QnDWBOM and MagicDisplay (AraDisplay) working.

As an example, here is a test page  [link]

Based Follow-up questions:

0) Which variables are people most eager to see?  (am assuming waveforms and similar health plots to what
     was available for ANITA)

1) To whom should he contact regarding inputting best/current calibration constants

  Ryan notes:  The point is, not only RF calibrations, but also other calibration values, such as RF power, temperature, etc.
and getting these into a meaningful, human-readable format.  Moreover, he offers the following:

"On the RF calibration front if people are too busy over there I have a
student who can help out. He has been looking into the ANITA-II
calibrations and has managed to recreate Abby's constants from
Palestine (trying to look into why the spread is of constants is
larger in ANITA-II than ANITA-I), and could in theory do the same with
the sine wave data you already have on tap."

2) Who would be the best person to ask questions about the data flow?

Summary from 29-NOV-2010:    [txt]   and references slides:

1) on testbed threshold scan efficiencies (Ben)  [PPT]

2) on calibration issues (Rishi)  [PDF]

24-NOV-2010 5pm (Hawaii/11am Taipei 25-NOV) Meeting:   [link]

  1. Further IRS testing at NTU
  2. Further discussion on calibration techniques
  3. Update on IRS2 delivery/paperwork

22-NOV-2010 1:30pm (regular) Meeting Agenda Items

     1 - ICRR FPGA Firmware Status (Patrick/Luca/Brendan)

          Additions since last week:

          . using the EXT_TRIG input to deliever the PPS signal from the Ru clock to the firmware
          . new counter (ROVCCA/ROVCCB) to count the internal clock ticks since the last PPS
          . trigger pattern in the event data

         Open Issues:

          . trigger type in the event data
          . check of the deadtime counter
          . fix to the PPS counter
          . test of the Batwing trigger / setting the coincidence window the Batwing trigger

         Bygone Issues That We Might Not Want to Forget About:

          . resurfacing of the LAB 'bad' waveform issue as a result of the kernal update done on ara2
          . anything else?
         
       2 - LAB3 Issues

          . skipped codes (Rishi/Andres/Kurtis/Luca/Gary)

     3 - SBC issues (Brendan/Ben/Peter)

          . what to do about the 'cold' memory problem?

          . automation of the startup + addition of a run number/run comment feature

     4 - Task List for the Freezer (Peter/Brendan/Ben)

          . discone trigger efficiency
          . batwing trigger efficiency
          . Ru clock PPS reset test
          . collect sine wave data
          . if time, change the temperature

     5 - This Week's Shipping Issue (Christian/Brian)

     6 - AOB

15-NOV-2010 week Meetings == GSV @ KEK (Brendan will run?)

10-NOV-2010 5pm (Hawaii/11am Taipei 11-NOV) Meeting:   [link]

  1. Receipt of Equalizer circuit (FR-4) and IRS_eval boards in Hawaii --> some test results posted
  2. Further IRS testing at NTU
  3. Further discussion on calibration techniques

8-NOV-2010 1:30pm (regular) Meeting Agenda Items

     1 - ICRR FPGA Firmware Status (Patrick/Luca/Brendan)

          .  the triggering issue in the current version of the firmware
          .  not to forget, the LAB readout issue remains to some extent (??)

     2 - Shipping (Christian/Brian/Peter/Brendan)

     3 - What's Left To Complete The TestBed  (Peter/Brendan/Ben)

          . plan for putting into the freezer (finally, maybe)

     4 - Status of the DAQ software from Ped  (Brendan)

     5 - What's Left To Complete The Full Signal Chain (Peter/Brendan/Ben)

     6 - Status of the calibration analysis (Brendan)

          . what do we want to have done before we freeze the system?

     7 - AOB

3-NOV-2010 5pm (Hawaii/11am Taipei 28-OCT) Meeting:   [link]

  1. Check on shipping confirmation on Equalizer circuit (FR-4) and IRS_eval boards to Hawaii.
  2. Further IRS testing at NTU
  3. Kurtis' presentation on "ellipse" sampling analysis

1-NOV-2010 1:30pm (regular) Meeting Agenda Items

     1 - ICRR FPGA Firmware Status (Patrick/Luca/Brendan)

          .  the triggering issue in the current version of the firmware
          .  not to forget, the LAB readout issue remains to some extent (??)

     2 - Shipping (Christian/Brian/Peter/Brendan)

     3 - What's Left To Complete The TestBed  (Peter/Brendan/Ben)

          . plan for putting into the freezer (finally, maybe)

     4 - Status of the DAQ software from Ped  (Brendan)

     5 - What's Left To Complete The Full Signal Chain (Peter/Brendan/Ben)

     6 - Status of the calibration analysis (Brendan)

          . what do we want to have done before we freeze the system?

     7 - AOB

27-OCT-2010 5pm (Hawaii/11am Taipei 28-OCT) Meeting:   [link]

  1. Check on shipping confirmation on Equalizer circuit (FR-4) and IRS_eval boards to Hawaii.
  2. IRS2 PO to MOSIS (updated Quotation received)
  3. Further IRS testing at NTU

25-OCT-2010 1:30pm (regular) Meeting Agenda Items

     1 - ICRR FPGA Firmware Status (Patrick/Luca/Brendan)

          .  the triggering issue in the current version of the firmware
          .  not to forget, the LAB readout issue remains to some extent (??)

     2 - Shipping (Christian/Brian/Peter/Brendan)

     3 - What's Left To Complete The TestBed  (Peter/Brendan/Ben)

          . plan for putting into the freezer (finally, maybe)

     4 - Status of the DAQ software from Ped  (Brendan)

     5 - What's Left To Complete The Full Signal Chain (Peter/Brendan/Ben)

     6 - Status of the calibration analysis (Brendan)

          . what do we want to have done before we freeze the system?

     7 - AOB

20-OCT-2010 5pm (Hawaii/11am Taipei 21-OCT) Meeting:   [link]

18-OCT-2010 1:30pm (regular) Meeting Agenda Items

     1 - ICRR FPGA Firmware Status (Patrick/Luca/Brendan)

          .  the triggering issue in the current version of the firmware (ELOG 45)
          .  not to forget, the LAB readout issue remains to some extent (??)

     2 - Shipping (Christian/Brian/Peter/Brendan)

     3 - What's Left To Complete The TestBed  (Peter/Brendan/Ben)

          . plan for putting into the freezer (finally, maybe)

     4 - Status of the DAQ software from Ped  (Brendan)

     5 - What's Left To Complete The Full Signal Chain (Peter/Brendan/Ben)

     6 - Status of the calibration analysis (Brendan)

          . what do we want to have done before we freeze the system?

     7 - AOB

ARA Station readout update (from Patrick 13-Oct)

DDA layout

13-OCT-2010 5pm (Hawaii/11am Taipei 23-SEP) Meeting:   [link]

11-OCT-2010 1:30pm (regular) Meeting Agenda Items

     1 - ICRR FPGA Firmware Status (Patrick/Luca/Brendan)

          . summary of where we are right now
          . debugging the LAB readout issue
          . discussion of how we want to proceed with the trigger testing.

     2 - Antenna Update (Christian/Brian/Peter)

          . what's done?  everything?

     3 - What's Left To Complete The TestBed  (Peter/Brendan/Ben)

          . status of testing
          . plan for putting into the freezer (finally, maybe)
          . update on the channel assignments as per ELOG -- DONE

     4 - Status of the DAQ software from Ped  (Brendan)

     5 - What's Left To Complete The Full Signal Chain (Peter/Brendan/Ben)

          . receiver boxes status

     6 - Status of the calibration analysis (Brendan)

          . status / plan for the 'pre-freezer' calibration

     7 - AOB

29-SEP-2010 6am (Hawaii/11am Madison) IRS Design Review:   [link]

29-SEP-2010 5pm (Hawaii/11am Taipei 23-SEP) Meeting:   [link]

27-SEP-2010 10am (morning) Meeting (with Patrick) Agenda Items:

UH Conference line number to call in: 

(808) 956-5610     1177#

A)  AMBER
     1 - AMBER Waiver update?
     2 - AOB?

A)  ARA -- next gen ARA readout (IRS) board
     1 - Schematics overview -- initial review Patrick/Gary
        Action item:  IRS2 pins:  (previously n.c. on IRS)     pin 33 = VDD;  pin 128 = GND   schematic  [PDF]
     2 - ICRR FPGA Firmware Status 
     3 - Discussion on schedule  --  try to submit by mid-October
     4 - Update on the Equalizer Status (didn't get to)

 For reference, latest version of readout Schematics from Patrick:

27-SEP-2010 1:30pm (regular) Meeting Agenda Items:

     0 - Update from morning review, NTU (IRS testing), IRS2 Design Review  [Gary]

     1 - ICRR FPGA Firmware Status (Patrick/Luca/Brendan)

          . required update for the trigger - remapping of discone channels & switch to negative-going signals
          . discussion of how we want to proceed with the testing.

     2 - Antenna Update (Christian/Brian/Peter)

          . what's done?
          . what testing is practical before shipping 2-3 weeks from now?

     3 - What's Left To Complete The TestBed  (Peter/Brendan/Ben)

          . status of the box -  have GPS, Rb-clock, 2nd amplifier stage for discone triggering in place; anything else?
          . plan for testing
          . plan for putting into the freezer (finally, maybe)
          . update on the channel assignments as per ELOG

     4 - Status of the DAQ software from Ped  (Brendan)

     5 - What's Left To Complete The Full Signal Chain (Peter/Brendan/Ben)

         . receiver boxes status
         . filters?

     6 - Status of the calibration analysis (Brendan)

           . what do we want to have done before we freeze the system?

     7 - AOB

20-SEP-2010 10am (morning) Meeting (with Patrick) Agenda Items:

A)  AMBER
     1 - AMBER Waiver update
     2 - Discussion of the Sun & CassA Analysis Work (Andres)  [PDF]
     3 - Status of the Auger Triggering Algorithm
     4 - AOB

A)  ARA
     1 - Schedule reminder
     2 - ICRR FPGA Firmware Status
     3 - Discussion of the DAQ Plan
     4 - ARA/IRS Board Design Discussion
     5 - Update on the Equalizer Status

20-SEP-2010 1:30pm (regular) Meeting Agenda Items:

      1 - ICRR FPGA Firmware Status

          . comments from the earlier call with Patrick
          . how's the merging effort going?
          . first results from testing Luca's latest firmware release?
          . discussion of how we want to procede with the testing.

     2 - Shipping Update (Christian/Brian)

     3 - Antenna Update (Christian/Brian/Peter)

     4 - Results of the Threshold Scans & Discussion About Fixing Both ICRR Boards  (Brendan/Ben/Peter)

          . ICRR_01 looks as if all the channels are working; need to hookup and do thorough test
          . ICRR_02 probably has one blown transformer (DISC03 channel) and the batwing channels need to be tested

     5 - What's Left To Complete The TestBed (Peter/Brendan/Ben)

         . the Ru-clock needs 15V, so we need to update the 12V DC-to-DC converter in the power box - DONE
         . we are going to put in the 2nd amplifier stage for the diode detectors - WORKING IN PROGRESS
         . install the GPS - WORKING IN PROGRESS
         . does anything else needs to be crammed into this box?
         . current channel assignments as per ELOG 38

     6 - Status of the DAQ software from Ped (Brendan)

     7 - What's Left To Complete The Full Signal Chain (Peter/Brendan/Ben)

         . receiver boxes status
         . filters?

     8 - Status of the calibration analysis (Brendan)

           . what do we want to have done before we freeze the system?

     9 - AOB

15-SEP-2010 5pm (Hawaii/11am Taipei 16-SEP) Meeting:   [link]

Request to follow-up on status of getting Equalizer circuit fabbed on FR-4.

13-SEP-2010 9:15am (morning) Meeting (with Patrick) Agenda Items:

UH Conference line number to call in (assuming same as subsequent/usual ANITA one): 

(808) 956-5610     1177#

     1 - Amber News
     2 - ICRR FPGA Firmware Status
     3 - Outline of the DAQ Plan (as per discussions with Ped on Thursday)
     4 - ARA/IRS Board Design Discussion
     5 - Update on the Equalizer Status

For reference:  IRS evaluation meeting (8pm PDT/5pm HST/11am Taiwan)  [meeting link]
    --> Update on Equalizer circuit for cable (Chih-Ching)  [PDF]

13-SEP-2010 1:30pm (regular) Meeting Agenda Items:

ID Lab number for anyone to call in:  (808) 956-2920

     1 - ICRR FPGA Firmware Status (just in case Luca cannot make the morning call)

          . how's the merging effort going?
          . first results from testing Luca's latest firmware release?
          . discussion of how we want to procede with the testing.

     2 - Shipping Update (Christian/Brian)

     3 - Antenna Update (Christian/Brian/Peter)

     4 - Results of the Threshold Scans & Discussion About Fixing Both ICRR Boards  (Brendan/Ben/Peter)

     5 - What's Left To Complete The TestBed (Peter/Brendan/Ben)

         . the Ru-clock needs 15V, so we need to update the 12V DC-to-DC converter in the power box
         . we are going to put in the 2nd 2nd amplifier stage for the diode detectors
         . current channel assignments as per ELOG 38

     6 - What's Left To Complete The Full Signal Chain (Peter/Brendan/Ben)

         . receiver boxes
         . filters?

     7 - Status of the calibration analysis

           . what do we want to have done before we freeze the system?

     8 - AOB

21-AUG-2010 Items:

The previously posted IRS Eval schematic was wrong!  Updated GSV
  1. IRS Eval Rev C  [PDF]

24-JUL-2010 Items:

Some papers on cable compensation of amplifier response, found by Peter:
  1. Compensation Filter circuit [PDF]
  2. Microstrip compensation filter technique [PDF]

28-JUN-2010 Items:

  1. Ped's proposal on HK Data format (v1) [PDF]
  2. ICRR/TRACR programming
  3. Comms standard for new DAQ option?

14-JUN-2010 Agenda:

  1. Brendan's threshold scan:
    1. Comments [txt] 
    2. Plots page [link]
  2. Questions/comments from Luca: [txt]
  3. Summaries from Luca on Firmware:
    1. TRACR <--> ICRR interface summary [txt]
    2. TRACR <--> DOM summary [txt]
  4. Test results (Brendan)  [link]
  5. Test items? 
  6. What to deploy this year?

News:

ARA firmware programming [link]

ARA Design Review/Testbed Engineering Review was held August 15-18, 2010 at the New Otani Kaimana Beach Hotel 

Design review documents posted under DocDB at  [link]
Hot Links:

Recent documentation:
  1. ARA Pulser PCBs repository  [link]
  2. DOR API (Kael) [PDF]
  3. Extremely useful set of IceRay era files (Hagar) [link]
  4. TRACR Programming (Hagar) [link]  
  5. Additional info:  JTAG boundary scan {XSVF generation/flasher IF} -- (John Kelley)  [link]
  6. Archive server copy of IceCube DAQ/Timing [PDF]
  7. Detailed RapCal write-up [ps]
  8. IceRay (1.8km) Cable documentation (Bob M.) [PDF]
  9. Comment from Bob M. on cable breakout/pins [txt]
  10. Cable emulator documentation: 
    1. 3km cable emulator [PDF] 
    2. Quad cable simulator [PDF]
    3. Cable emulator parts [PDF]
  11. ICRR schematics [PDF] (CF ARA ELOG #17)
    1. USB interface board schematics [PDF]
  12. DOR card driver (Hagar 14-MAY-2010) [rpm]
  13. Schedule reference (Albrecht 22-APR-2010) [PDF]
  14. kick-off meeting Indico [webpage]
  15. ASIC of reference: IRS design [homepage]
  16. IceRay Testing Reference (John Kelley)
    1. IceRay Integration visit [website]
    2. Flasher board [link]
    3. Mini how-to document [PDF]

Testing task list:


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Last modified: 1/15/2013