From allison.122@osu.edu Wed May 11 05:15:40 2011 Date: Wed, 11 May 2011 11:14:38 -0400 From: Patrick Allison To: ara-firm@ara.icecube.wisc.edu, Peter Gorham Subject: [Ara-firm] ATRI status update All (Peter should really be added to this list...): We now have an FX2 development board attached to the populated ATRI rev A, and have further verified: 1) the hot-swap controller's voltage and current monitoring and the switch on/off ability 2) the clock multiplier (Si5367)'s operation The clock multiplier took a bit of work, because there's no "Getting Started with DSPLL Chips" guide, so I may write up a quick document and put it on DocDB on how to handle these guys. However, the short version is: The way they work is by taking an input clock (call it CKIN), divide it down by a programmable amount (N3), and then compare the phase/frequency of that clock (CKIN/N1) to the phase of an internal digitally-controlled oscillator (DCO) running at between 4.85-5.67 GHz, divided down by a programmable amount (N2) - the DCO's frequency/phase are altered to minimize that difference, so basically the DCO runs at "CKIN*(N2/N3)". The DCO is also divided down by a programmable high-speed divider (N1_HS) and then the outputs are divided down by 5 independent lower-speed dividers (NC1-NC5), so the output becomes "CKOUT[i]=(CKIN*(N2/N3))/(N1_HS*NC[i])". SiLabs has a "DSPLLSim" program for determining all this stuff - one point to note is that while we're using an Si5368 for the first few boards due to availability, you *have* to use DSPLLSim set up as if you were using an Si5367, otherwise it simply won't work. This is *not documented anywhere*. For our 'nominal' configuration the values are: N3 = 1 (for all inputs) N2 = 500 N1_HS = 5 NC1 = 40 NC2 = 40 NC3 = 40 NC4 = 40 NC5 = 10 So in that case, the input is 10 MHz, DCO's running at 5 GHz, the 4 output clocks to the daughterboards are 25 MHz, and the FPGA clock is 100 MHz. Also the other thing I found is that the Si5368 has several bits in registers which are labelled as "reserved" and marked as "read-only." This doesn't mean you *can't* write to them. It means you *should not* write to them. Apparently those bits are "make the entire chip work." :) Again, not documented anywhere. Fun. Last few things we're going to do are populate a daughterboard connector and make sure everything's okay there, and then try to wire up the FX2LP to try to test programming the FPGA via USB. Patrick _______________________________________________ Ara-firm mailing list Ara-firm@ara.icecube.wisc.edu http://ara.icecube.wisc.edu/mailman/listinfo/ara-firm