In this textfile a simple mapping of the TRACR-ICRR interface signals (and their
meaning with respect to the working of the ICRR module) is 
described. Signals are followed from downstream to upstream, and for each of
them a brief intuitive description is provided as well.

Notes: 
1. Most internal signals are preceded by an 'x' that is omitted in this list.
2. Signals named *signal* do not have a specific name but are used directly.
3. Almost always the same internal names are used inside the TRACR 
I/O interface. Exceptions: FROM_TRACR and IO_TRACR are called TO_ICRR and
FROM_ICRR in the TRACR firmware. CTL0 is called DONE in TRACR (no name
in ICRR).

+-----------------------+-----------------------------------------------+
|TRACR Signal Name	| Internal signal name	| function		|
+-----------------------+-----------------------------------------------+
INPUTS:
+-----------------------+-----------------------------------------------+
|PA0			| SOFT_TRIG		| Software generated 	|	
|			|			| trigger: only	|
|			|			| trigger active now 	|
+-----------------------+-----------------------+-----------------------+
|PA1			| CAL_PULSER		| External trigger 	|	
|   			| 			| as SOFT_TRIG, but 	|	
|   			| 			| passes through a  	|	
|   			| 			| square wave gen. 	|	
+-----------------------+-----------------------+-----------------------+
|PA2			| FORCE_CLR		| External global CLR 	|	
|   			| 			| - restarts ICR_MESS 	|	
|   			| 			| - init. LAB3 		|	
|   			| 			| Same funct. as CTL0	|	
+-----------------------+-----------------------+-----------------------+
|PA3			| ENABLE_CNT		| Enable event counter 	|	
|			| 			| (that counts # NRUNA)	|	
+-----------------------+-----------------------+-----------------------+
|PA4			| RESET_CNT		| Resets event counter 	|	
+-----------------------+-----------------------+-----------------------+
|PA5			| *enable_ref*		| Enables refer. clock 	|	
|			| 			| (TRIG_REF_A,B,C) 40MHz|	
+-----------------------+-----------------------+-----------------------+
|PA6			| STRB_A_DAC		| On the falling edge, 	|	
|			| 			| samples DAC_DATA into	|	
|			| 			| xDAC_A  (ref. DAC)	|	
+-----------------------+-----------------------+-----------------------+
|PA7			| STRB_B_DAC		| As above for B 	|	
+-----------------------+-----------------------+-----------------------+
|RELIC1			| STRB_C_DAC		| As above for C 	|	
+-----------------------+-----------------------+-----------------------+
|RELIC2			| STRB_D_DAC		| As above for D 	|	
+-----------------------+-----------------------+-----------------------+
|RELIC3			| STRB_E_DAC		| As above for E 	|	
+-----------------------+-----------------------+-----------------------+
|RELIC4			| STRB_F_DAC		| As above for F 	|	
+-----------------------+-----------------------+-----------------------+
|RELIC5			| LOAD_DACS		| Starts DAC_TIMING and	|	
|			| 			| (eventually) forces 	|	
|			| 			| updating of all 	|	
|			| 			| reference DAC values	|	
+-----------------------+-----------------------+-----------------------+
|RELIC6			| STRB_DATA		| General READ CLOCK! 	|	
|			| 			| Used by ICRR_MESS 	|	
|			| 			| To transmit all the 	|	
|			| 			| data from ICRR. 	|	
|			| 			| Perfectly synchr. 	|	
|			| 			| With DOM (TRACR clk 	|	
|			| 			| is bypassed from DOM	|	
+-----------------------+-----------------------+-----------------------+
|CTL0			| *alternate CLR*	| In OR with PA2: gen. 	|	
|			| 			| clear 		|	
+-----------------------+-----------------------+-----------------------+
|CTL1			| DOM_CLK		| Left open. Could be 	|	
|			| 			| used to derive the 	|	
|			| 			| ICRR clock from DOM 	|	
+-----------------------+-----------------------+-----------------------+
|CTL2			| TOGGLE		| Used in TRACR_IO to 	|	
|			| 			| indicate direction of |	
|			| 			| bi-dir. pads (FD0-15) |	
|			| 			| CTL2='1' from TRACR	|	
|			| 			| CTL2='0' to TRACR	|	
+-----------------------+-----------------------+-----------------------+
|RDY0			| HK_ONLY		| Controls transmission |	
|			| 			| of data: if '1' only  |	
|			| 			| hosekeeping 		|	
+-----------------------+-----------------------+-----------------------+
|RDY1			| *open*		| Spare? 		|	
+-----------------------+-----------------------+-----------------------+
OUTPUTS:
+-----------------------+-----------------------------------------------+
|CLKOUT			| CLR_ALL		| Misleading name! 	|	
|			| 			| Not a clock but the 	|	
|			| 			| internally generated  |	
|			| 			| clear from PROGRESET 	|	
|			| 			| at startup or as a	|
|			| 			| consequence of asynch	| 
|			| 			| reset. 		|
+-----------------------+-----------------------------------------------+
|WAKEUP			| START 		| Indication of start	|	
|			|(DATA_READY in LAB3TOP)| acquisition from LABA | 
+-----------------------+-----------------------------------------------+
|IFCLK			| CLK   		| Internal 40MHz main 	|	
|			|			| cloc: used for synchr.| 
|			|			| TRACR			| 
+-----------------------+-----------------------------------------------+
|EXT_TRIG		| EXT_TRIG   		| External trigger 	|	
|			|			| Note: the ext. trigger| 
|			|			| is fed through a 	|
|			|			| separate coax. 	|
+-----------------------+-----------------------------------------------+
|SMB_TIMING		| PULSE   		| "Pulsed" NRUN using 	|	
|			|			| internal clock. 	| 
|			|			| Note: NOT going to	| 
|			|			| TRACR but to DOM 	| 
|			|			| dedicated cable 	| 
+-----------------------+-----------------------------------------------+
BI-DIRECTIONAL:
+-----------------------+-----------------------------------------------+
|FD0-15			| FROM_TRACR (CTL0='1')	| Input from TRACR	|	
|			| TO_TRACR (CTL0='0')	| Output to TRACR	|	
+-----------------------+-----------------------------------------------+