klm_scint.vhd

----------------------------------------------------------------------------------
-- KLM SCROD firmware
----------------------------------------------------------------------------------
library ieee;
   use ieee.std_logic_1164.all;
   use ieee.numeric_std.all;
   use ieee.std_logic_unsigned.all;
   use ieee.std_logic_misc.all;
library unisim;
   use unisim.vcomponents.all;
library unimacro;
   use unimacro.vcomponents.all;
use work.all;
   use work.tdc_pkg.all;
   use work.time_order_pkg.all;
   use work.conc_intfc_pkg.all;
   use work.klm_scrod_pkg.all;
   use work.klm_scint_pkg.all;




entity klm_scint is
    generic (
       NUM_GTS                  : integer := 1;
       B2TT_SIM_SPEEDUP         : std_logic := '0';
       IS_SIM                   : std_logic := '0';
       SLOW_CTRL_BUFF           : integer := 7;
       -- VERSION                  : std_logic_vector(15 downto 0) := X"0C06" -- dedicated sps_reset
       -- VERSION                  : std_logic_vector(15 downto 0) := X"0C07" -- add charge calc to FE block and sps 
       -- VERSION                  : std_logic_vector(15 downto 0) := X"0C08" -- add reset debug to regs -- verified resetft issues b2tt_runreset, and none others
       -- VERSION                  : std_logic_vector(15 downto 0) := X"0C09" -- rm rst dbg. reduce sps bram size. switch metric to le_charge. switch to 128 samples.
       -- VERSION                  : std_logic_vector(15 downto 0) := X"0C0A" -- added self_trig mode, refactored mode multiplexing, connected trig_proc_cnt, added quick-send of null hits
       -- VERSION                  : std_logic_vector(15 downto 0) := X"0C0B" -- changed ped measure to have predefiend hold time for analog samples, added padding to sampling mask
       -- VERSION                  : std_logic_vector(15 downto 0) := X"0C0C" -- fix trig_asic[0:9]to[1:10] mapping bug. fix intermittent no-debug-wave bug(?). switch to 128 ped avgs.
       -- VERSION                  : std_logic_vector(15 downto 0) := X"0C0D" -- no ftsw trig modes caused rx_features to hang -- moved lgc to pkt sending. Use newmask on tb5 evts only, ftsw or self trig only. 
       -- VERSION                  : std_logic_vector(15 downto 0) := X"0C0E" -- Fix bug: HitData.first_hit was being dropped before writing to qt_fifo
       -- VERSION                  : std_logic_vector(15 downto 0) := X"0C0F" -- inc. trg_proc_cnt for null hits; temp fake pkt for null trigs; zero i_vectrgbits after force trig
       -- VERSION                  : std_logic_vector(15 downto 0) := X"0C10" -- add width to force trig bits, simplify calcROI handshake
       -- VERSION                  : std_logic_vector(15 downto 0) := X"0C11" -- trig_queue bug fixes, add 2 bits to daq packet
       -- VERSION                  : std_logic_vector(15 downto 0) := X"0C12" -- lookback tuning, queue getting full thresh
       -- VERSION                  : std_logic_vector(15 downto 0) := X"0C13" -- fix rd_stale bug.
       -- VERSION                  : std_logic_vector(15 downto 0) := X"0C14" -- add diff proc counts. simplify CalculateROI.
       -- VERSION                  : std_logic_vector(15 downto 0) := X"0C15" -- fix new_mask bug, missing default when tb5!='1'. Also BUS_RD_WINSEL was disconnected somehow.
       -- VERSION                  : std_logic_vector(15 downto 0) := X"0C16" -- Removed redundant OTHERS states. Rep. self trg w/ not ftsw trg. Modify rd_stale lgc.
       -- VERSION                  : std_logic_vector(15 downto 0) := X"0C17" -- Simplify lgc in ProcWaveform:LOOPING_JOBS 
       VERSION                  : std_logic_vector(15 downto 0) := X"FE00" -- Move HitDataSerializer to WaveformReadout_i
    );
    port (
        -- LEDS                     : inout STD_LOGIC_VECTOR(12 downto 3);
        force_trig : in std_logic; -- sim only
        TTDCLKP                  : in  std_logic;
        TTDCLKN                  : in  std_logic;
        TTDACKP                  : out std_logic;
        TTDACKN                  : out std_logic;
        TTDTRGP                  : in  std_logic;
        TTDTRGN                  : in  std_logic;
        TTDRSVP                  : out std_logic;
        TTDRSVN                  : out std_logic;

        mgttxfault               : in std_logic_vector(1 to NUM_GTS);
        mgtmod0                  : in std_logic_vector(1 to NUM_GTS);
        mgtlos                   : in std_logic_vector(1 to NUM_GTS);
        mgttxdis                 : out std_logic_vector(1 to NUM_GTS);
        mgtmod2                  : out std_logic_vector(1 to NUM_GTS);
        mgtmod1                  : out std_logic_vector(1 to NUM_GTS);
        mgtrxp                   : in std_logic;
        mgtrxn                   : in std_logic;
        mgttxp                   : out std_logic;
        mgttxn                   : out std_logic;
        mgtclk0p                 : in std_logic;
        mgtclk0n                 : in std_logic;
        mgtclk1p                 : in std_logic;
        mgtclk1n                 : in std_logic;

        -- EX_TRIGGER_MB                 : out std_logic;
        -- EX_TRIGGER_SCROD            : out STD_LOGIC;

        --Global Bus Signals

        ----- ASIC related ports ------
        -- BUS_REGCLR               : out std_logic;
        BUSA_WR_ADDRCLR          : out std_logic;
        BUSA_RD_ENA              : out std_logic;
        BUSA_RD_ROWSEL           : out std_logic_vector(2 downto 0);
        BUSA_RD_COLSEL           : out std_logic_vector(5 downto 0);
        BUSA_CLR                 : out std_logic;
        BUSA_RAMP                : out std_logic;
        BUSA_SAMPLESEL           : out std_logic_vector(4 downto 0);
        BUSA_SR_CLEAR            : out std_logic;
        BUSA_SR_SEL              : out std_logic;
        BUSA_DO                  : in  std_logic_vector(14 downto 0);

        BUSB_WR_ADDRCLR          : out std_logic;
        BUSB_RD_ENA              : out std_logic;
        BUSB_RD_ROWSEL           : out std_logic_vector(2 downto 0);
        BUSB_RD_COLSEL           : out std_logic_vector(5 downto 0);
        BUSB_CLR                 : out std_logic;
        BUSB_RAMP                : out std_logic;
        BUSB_SAMPLESEL           : out std_logic_vector(4 downto 0);
        BUSB_SR_CLEAR            : out std_logic;
        BUSB_SR_SEL              : out std_logic;
        BUSB_DO                  : in  std_logic_vector(14 downto 0);

        SIN                      : out std_logic_vector(9 downto 0);
        PCLK                     : out std_logic_vector(9 downto 0);
        SHOUT                    : in  std_logic_vector(9 downto 0);
        SCLK                     : out std_logic_vector(9 downto 0);

        WL_CLK_N                 : out std_logic_vector(9 downto 0);
        WL_CLK_P                 : out std_logic_vector(9 downto 0);
        WR1_ENA                  : out std_logic_vector(9 downto 0);
        WR2_ENA                  : out std_logic_vector(9 downto 0);

        SSTIN_N                  : out std_logic_vector(9 downto 0);
        SSTIN_P                  : out std_logic_vector(9 downto 0);

        SR_CLOCK                 : out std_logic_vector(9 downto 0);
        SAMPLESEL_ANY            : out std_logic_vector(9 downto 0);

        BUSA_SCK_DAC             : out std_logic;
        BUSA_DIN_DAC             : out std_logic;
        BUSB_SCK_DAC             : out std_logic;
        BUSB_DIN_DAC             : out std_logic;

        TARGET_TB                : in tb_vec_type;

        TDC_CS_DAC               : out std_logic_vector(9 downto 0);

        TDC_AMUX_S               : out std_logic_vector(3 downto 0);

        TOP_AMUX_S               : out std_logic_vector(3 downto 0);

        RAM_ADDR                 : out std_logic_vector(21 downto 0);  -- RAM address line
        RAM_IO                   : inout std_logic_vector(7 downto 0);  -- tristate buffer below, use RAM_din or RAM_do, select with RAM_rw
        RAM_CEb                  : out std_logic;
        RAM_CE                   : out std_logic;
        RAM_OEb                  : out std_logic;
        RAM_WEb                  : out std_logic

        -- --! MPPC ADC
        -- SCL_MON                  : out STD_LOGIC;
        -- SDA_MON                  : inout STD_LOGIC

        -- TDC_DONE                 : in STD_LOGIC_VECTOR(9 downto 0); -- move to readout signals
        -- TDC_MON_TIMING           : in STD_LOGIC_VECTOR(9 downto 0)  -- add the ref to the programming of the TX chip
    );
end klm_scint;


architecture Behavioral of klm_scint is

-- SYNCHRONOUS SIGNALS BY PROCESS WHICH DRIVES THEM

    signal b2tt_b2clkup_r       : std_logic;
    signal b2tt_b2ttup_r        : std_logic;
    signal b2tt_b2ttup_2r       : std_logic;
    signal b2tt_regdbg          : std_logic_vector(7 downto 0) := (others => '0');

    signal ScrodStatus          : KlmScrodStatusType := KlmScrodStatusType0;

    -- signal i_trgon               : std_logic := '1';

    -- rst_conc_intfc_on_startup:
    signal klmifc_reset         : std_logic := '0';
    signal klmifc_reset_done    : std_logic := '0';

    signal klm_status_regs_r      : stat_reg_type;



-- SIGNALS DRIVEN BY INSTANTIATED ENTITIES

    signal clk                  : std_logic := '0';
    signal clkinv               : std_logic := '0';
    signal clk2x                : std_logic := '0';
    signal b2tt_b2clkup         : std_logic;
    signal b2tt_b2ttup          : std_logic;
    signal b2tt_trgout          : std_logic;
    signal b2tt_sigbit2         : std_logic_vector(1 downto 0);
    signal b2tt_trgtag          : std_logic_vector(31 downto 0);
    signal b2tt_utime           : std_logic_vector(B2TT_NBITTIM-1 downto 0);
    signal b2tt_ctime           : std_logic_vector(26 downto 0) := (others=>'0');
    signal b2tt_divclk1         : std_logic_vector(1 downto 0);
    signal b2tt_divclk2         : std_logic_vector(1 downto 0);
    signal b2tt_runreset        : std_logic := '1';
    signal b2tt_feereset        : std_logic := '1';
    signal b2tt_gtpreset        : std_logic := '1';
    signal b2tt_b2lreset        : std_logic := '1';
    signal b2tt_b2ttver         : std_logic_vector(15 downto 0);
    signal b2tt_fifordy         : std_logic                             := '0';
    signal b2tt_fifodata        : std_logic_vector(95 downto 0)         := (others => '0');
    signal b2tt_exprun          : std_logic_vector(31 downto 0);
    signal b2tt_frame           : std_logic;
    signal b2tt_frame9          : std_logic;
    signal b2tt_dbglink         : std_logic_vector (95 downto 0)        := (others => '0');


    signal b2tt_b2linkwe        : std_logic                             := '0';
    signal b2tt_fifonext        : std_logic                             := '0';
    signal rcl_src_rdy_n        : std_logic;
    signal rcl_data             : std_logic_vector(15 downto 0);
    signal aurora_stat          : Aurora_Status_t;
    signal i_qt_fifo_rd_en       : std_logic;
    signal i_exttb              : tb_vec_type;
    signal stat_tx_in_progress  : std_logic;
    -- signal b2tt_b2plllk         : std_logic;
    -- signal rcl_sof_n            : std_logic;
    -- signal rcl_eof_n            : std_logic;


    signal ScrodConfig          : KlmScrodConfigType := KlmScrodConfigZero;
    signal ScrodControl         : KlmScrodControlType;
    signal klm_status_regs      : stat_reg_type;
    -- signal rcl_dst_rdy_n        : std_logic;


    signal i_qt_fifo_d           : std_logic_vector(17 downto 0);
    signal i_qt_fifo_empty       : std_logic;
    signal i_qt_fifo_evt_rdy     : std_logic;


    signal asic_sin             : std_logic := '0';
    signal asic_pclk            : std_logic := '0';
    signal asic_sclk            : std_logic := '0';


    signal SCK_DAC         : std_logic := '0';
    signal DIN_DAC         : std_logic := '0';


    -- --!  mppc_current_measurement (Module_ADC_MCP3221_I2C_new):
    -- signal i_sda_mon             : std_logic := '0';
    -- signal i_scl_mon             : std_logic := '0';


    signal wilk_clk              : std_logic_vector(9 downto 0)  := (others => '0');

-- SINALS DRIVEN ASYNCHRONOUSLY
    signal b2tt_ctime_i         : std_logic_vector(26 downto 0) := (others=>'0');
    signal b2tt_trig            : std_logic;
    signal i_force_trig         : std_logic;

begin




--------------------- ASYNCHRONOUS LOGIC ---------------------------------------------
    ScrodStatus.Version <= VERSION;
    ScrodStatus.Shout <= SHOUT(9 downto 0);
    ScrodStatus.aurora_stat <= aurora_stat;
    RAM_CE <= '1';
    RAM_CEb <= '0';
    BUSA_SCK_DAC <= SCK_DAC;
    BUSB_SCK_DAC <= SCK_DAC;
    BUSA_DIN_DAC <= DIN_DAC;
    BUSB_DIN_DAC <= DIN_DAC;
    --Only specified ASIC gets serial data signals, uses bit mask
    -- TODO : add asics number as a generic of tx_dac_control
    --        and move below lines to the entity
    gen_DAC_CONTROL: for i in 0 to 9 generate
        SIN(i) <= asic_sin  and ScrodConfig.TxRegCtrlMask(i);
        PCLK(i) <= asic_pclk and ScrodConfig.TxRegCtrlMask(i);
        SCLK(i) <= asic_sclk and ScrodConfig.TxRegCtrlMask(i);
    end generate gen_DAC_CONTROL;

    sim_true: if IS_SIM = '1' generate
        process(clk, b2tt_ctime_i)
        begin
            if rising_edge(clk) then
                b2tt_ctime_i <= b2tt_ctime_i + '1';
            end if;
        end process;
        b2tt_trig <= b2tt_sigbit2(0);
        i_force_trig <= force_trig;
    end generate;

    sim_false: if IS_SIM = '0' generate
        b2tt_ctime_i <= b2tt_ctime;
        b2tt_trig <= b2tt_trgout;
        i_force_trig <= ScrodControl.force_trig;
    end generate;


--------------------- SYNCHRONOUS LOGIC ---------------------------------------------
    startup_latch_proc: process(clk, b2tt_utime, b2tt_b2clkup, b2tt_b2ttup,
                                b2tt_b2ttup_r, b2tt_b2ttup_2r, ScrodControl.B2ttDbg)
        variable i_utime_latched : std_logic := '0';
    begin
       if rising_edge(clk) then
          if i_utime_latched = '0' and b2tt_utime /= X"0000_0000" then
             ScrodStatus.StartUTime <= b2tt_utime;
             ScrodStatus.B2ttUpUTime <= b2tt_utime;
             i_utime_latched := '1';
          end if;
          b2tt_b2clkup_r <= b2tt_b2clkup;
          b2tt_b2ttup_r <= b2tt_b2ttup;
          b2tt_b2ttup_2r <= b2tt_b2ttup_r;
          if b2tt_b2ttup_2r /= b2tt_b2ttup_r then
             ScrodStatus.B2ttUpUTime <= b2tt_utime;
          end if;
          ScrodStatus.CurUTime <= b2tt_utime;
          b2tt_regdbg(5 downto 0) <= ScrodControl.B2ttDbg;
       end if;
    end process;



    b2tt_dbg2reg_proc: process (clk)
    begin
       if rising_edge(clk) then
          ScrodStatus.B2ttStaIddr <= b2tt_dbglink(23 downto 22);
          ScrodStatus.B2ttCntIdelay <= b2tt_dbglink(64 downto 58);
          ScrodStatus.B2ttUp <= b2tt_b2ttup;
          ScrodStatus.B2ClkUp <= b2tt_b2clkup;
       end if;
    end process;



    -- trgon_sw_4scaler_mode: process(clk)
    -- begin
    --    if rising_edge(clk) then
    --       if ScrodConfig.ReadoutMode = X"3" then
    --          i_trgon <= '0';
    --       else
    --          i_trgon <= '1';
    --       end if;
    --    end if;
    -- end process;



    rst_conc_intfc_on_startup: process (clk, b2tt_runreset)
    begin
       if rising_edge(clk) then
          if klmifc_reset_done = '1' then
             klmifc_reset <= b2tt_runreset;
          else
             klmifc_reset <= '1';
             klmifc_reset_done <= '1';
          end if;
       end if;
    end process;



    stat_reg_ppln: process(clk, klm_status_regs)
    begin
        if rising_edge(clk) then
            klm_status_regs_r <= klm_status_regs;
        end if;
    end process;



    -- asic_and_channel_multiplexer_for_mppc_current_measurement: process(clk, ScrodConfig.MppcAdcAsicN, ScrodConfig.MppcAdcChanN)
    -- begin
    --    if rising_edge(clk) then
    --       TDC_AMUX_S <= ScrodConfig.MppcAdcAsicN;   -- channel within daughter card
    --       TOP_AMUX_S <= ScrodConfig.MppcAdcChanN;   -- daughter number FIXME: AsicN and ChanN are mixed up
    --    end if;
    -- end process;




--------------------- MODULE INSTANTIATIONS ---------------------------------------------
    b2tt_i : entity work.b2tt
    generic map(
        SUBSYSTEM              => B2TT_SUBSYSTEM,
        FWTYPE                 => B2TT_FWTYPE,
        VERSION                => B2TT_VERSION,
        B2TT_VER               => B2TT_B2TT_VER,
        PROTOCOL               => B2TT_PROTOCOL,
        COMPAT                 => B2TT_COMPAT,
        DEFADDR                => B2TT_DEFADDR,
        FLIPCLK                => B2TT_FLIPCLK,
        FLIPTRG                => B2TT_FLIPTRG,
        FLIPACK                => B2TT_FLIPACK,
        USEFIFO                => B2TT_USEFIFO,
        CLKDIV1                => B2TT_CLKDIV1,
        CLKDIV2                => B2TT_CLKDIV2,
        USEPLL                 => B2TT_USEPLL,
        USEICTRL               => B2TT_USEICTRL,
        NBITTIM                => B2TT_NBITTIM,
        NBITTAG                => B2TT_NBITTAG,
        B2LRATE                => B2TT_B2LRATE,
        USEEXTCLK              => B2TT_USEEXTCLK,
        USE254IN               => B2TT_USE254IN, --
        SIM_SPEEDUP            => B2TT_SIM_SPEEDUP)
    port map(
        b2ttver                 => b2tt_b2ttver,
        --- RJ-45
        clkp                    => TTDCLKP,
        clkn                    => TTDCLKN,
        trgp                    => TTDTRGP,
        trgn                    => TTDTRGN,
        rsvp                    => TTDRSVP,
        rsvn                    => TTDRSVN,
        ackp                    => TTDACKP,
        ackn                    => TTDACKN,
        --- alternative external clock source
        extclk                  => '0',
        extclkinv               => '0',
        extclkdbl               => '0',
        extdblinv               => '0',
        extclklck               => '0',
        --- board id
        id                      => X"00FF", -- Use MSB for MB because RPC FEBs use LSB !How does this board get address?
        -- user status register (for debug)
        usrreg                  => open,
        usrdat                  => X"0000",
        --- link status
        b2clkup                 => b2tt_b2clkup,
        b2ttup                  => b2tt_b2ttup,
        --- system clock and time
        sysclk                  => clk,
        sysclkinv               => clkinv,
        rawclk                  => open,
        dblclk                  => clk2x,
        hlfclk                  => open,
        utime                   => b2tt_utime,
        ctime                   => b2tt_ctime,
        --- divided clock
        divclk1                 => b2tt_divclk1,
        divclk2                 => b2tt_divclk2,
        --- exp- / run-number
        exprun                  => b2tt_exprun,
        running                 => open,
        --- run reset
        runreset                => b2tt_runreset,
        feereset                => b2tt_feereset,
        b2lreset                => b2tt_b2lreset,
        gtpreset                => b2tt_gtpreset,
        rstmask                 => open, -- for runreset
        --- trigger
        trgout                  => b2tt_trgout,
        trgtyp                  => open,
        trgtag                  => b2tt_trgtag,
        trgmask                 => open,
        --- revolution
        frame                   => b2tt_frame,
        --revo3                 => open,
        frame9                  => b2tt_frame9,
        revoloc                 => open,
        revosig                 => open, -- TBI,
        abortgap                => open, -- TBI,
        injveto                 => open,
        injkick                 => open,
        injvpos                 => open,
        injvpre                 => open,
        injvlen                 => open,
        injvfull                => open,
        injvgate                => open,
        --- busy and status return
        busysrc                 => X"00", -- to suspend the trigger
        feeerr                  => X"00", -- to stop the run
        --- Belle2link status
        b2plllk                 => aurora_stat.gtlock,
        b2linkup                => '1',
        b2linkwe                => b2tt_b2linkwe,
        b2lclk                  => clk,
        --- SEM status (virtex5_seu_controller or SEU mitigation ipcore)
        semscan                 => '0',  -- end_of_scan / watchdog  (=> 1 bit)
        semdet                  => '0',  -- seu_detect / corrected  (=> 2 bit counter)
        semmbe                  => '0',  -- mbe/uncorrectable
        semcrc                  => '0',  -- crc_error (virtex5 only) (=> combined)
        --- data for Belle2link header
        fifordy                 => b2tt_fifordy,
        fifodata                => b2tt_fifodata,
        fifonext                => b2tt_fifonext,
        --- b2tt-link status
        regdbg                  => b2tt_regdbg, --X"00",
        octet                   => open,  -- decode
        isk                     => open,  -- decode
        cntbit2                 => open,  -- decode
        sigbit2                 => b2tt_sigbit2, --open,  -- decode
        dbglink                 => b2tt_dbglink,
        dbgerr                  => open
    );
    

    KLM_Interface_i : entity work.klm_intfc
    generic map(
        NUM_GTS    => NUM_GTS
    )
    port map (
        sysclk          => clk,
        sysclk2x        => clk2x,
        
        b2tt_b2clkup    => b2tt_b2clkup,
        -- b2tt_b2ttup     => b2tt_b2ttup,
        -- b2tt_trig     => b2tt_trig,
        -- b2tt_b2plllk    => b2tt_b2plllk,
        b2tt_ctime      => b2tt_ctime_i,
        b2tt_divclk1    => b2tt_divclk1,
        b2tt_divclk2    => b2tt_divclk2,
        b2tt_runreset   => klmifc_reset,
        -- b2tt_feereset   => b2tt_feereset,
        b2tt_gtpreset   => b2tt_gtpreset,
        b2tt_b2linkwe   => b2tt_b2linkwe,
        -- b2tt_b2lreset   => b2tt_b2lreset,
        b2tt_fifordy    => b2tt_fifordy,
        b2tt_fifodata   => b2tt_fifodata,
        b2tt_fifonext   => b2tt_fifonext,
        b2tt_frame      => b2tt_frame,
        b2tt_trgtag     => b2tt_trgtag,
        
        
        ----     ASIC Interface
        target_tb       => target_tb,    --  in tb_vec_type;
        
        -- SFP interface
        mgttxfault      => mgttxfault,
        mgtmod0         => mgtmod0,
        mgtlos          => mgtlos,
        mgttxdis        => mgttxdis,
        mgtmod2         => mgtmod2,
        mgtmod1         => mgtmod1,
        mgtclk0p        => mgtclk0p,
        mgtclk0n        => mgtclk0n,
        mgtclk1p        => mgtclk1p,
        mgtclk1n        => mgtclk1n,
        mgtrxp          => mgtrxp,
        mgtrxn          => mgtrxn,
        mgttxp          => mgttxp,
        mgttxn          => mgttxn,
        sfp_stat        => ScrodStatus.sfp_stat,
        aurora_stat     => aurora_stat,
        
        -- run control signals TODO : pack it into a record
        -- rcl_dst_rdy_n    => rcl_dst_rdy_n,
        -- rcl_sof_n        => rcl_sof_n,
        -- rcl_eof_n        => rcl_eof_n,
        rcl_src_rdy_n    => rcl_src_rdy_n,
        rcl_data         => rcl_data,
        
        qt_fifo_rd_en   => i_qt_fifo_rd_en,
        qt_fifo_rd_d    => i_qt_fifo_d,
        qt_fifo_empty   => i_qt_fifo_empty,
        qt_fifo_evt_rdy => i_qt_fifo_evt_rdy,
        
        -- trgon           => i_trgon, -- on/off trg path processing
        trgon           => '1', --#CK
        exttb           => i_exttb, -- trgbit pass through
        
        klm_status_upd  => ScrodControl.KlmStatusUpdate,
        stat_tx_in_progress => stat_tx_in_progress, --out
        klm_status_regs => klm_status_regs_r   --in
    );
        

        
    Register_Control_i : entity work.KLMScrodRegCtrl
    port map(
        clk => clk,
        -- rst => b2tt_runreset,
        
        -- rcl_dst_rdy_n  => rcl_dst_rdy_n,
        -- rcl_sof_n      => rcl_sof_n,
        -- rcl_eof_n      => rcl_eof_n,
        rcl_src_rdy_n  => rcl_src_rdy_n,
        rcl_data       => rcl_data,
        
        ScrodConfig    => ScrodConfig,   -- configuration
        ScrodControl   => ScrodControl,  -- control signals to update TX and MPPC regs
        ScrodStatus    => ScrodStatus,
        
        klm_status_regs => klm_status_regs,
        stat_tx_in_progress => stat_tx_in_progress
    );


        
    Readout_Control_i : entity work.KLMReadoutCtrl
    port map(
        clk              => clk,
        rst              => b2tt_runreset,
        
        trg              => b2tt_trig, -- trigger signal from b2tt
        trgtag           => b2tt_trgtag, -- trigger tag (event number)
        ctime            => b2tt_ctime_i,  -- current ctime
        
        vectrgbits       => i_exttb,     -- trigger bits from all asics
        
        -- daq interface
        qt_fifo_rd_en    => i_qt_fifo_rd_en,
        qt_fifo_dout     => i_qt_fifo_d,
        qt_fifo_empty    => i_qt_fifo_empty,
        qt_fifo_evt_rdy  => i_qt_fifo_evt_rdy,
        
        ScrodConfig      => ScrodConfig,
        force_trig       => i_force_trig,
        sps_reset        => ScrodControl.sps_reset,
        scalers_reset    => ScrodControl.TBScalersReset,
        
        -- status outputs
        scalers_busy     => ScrodStatus.TbScalersBusy,
        scalers_ch_arr   => ScrodStatus.TbScalersChnArr,
        -- tbfifo_cnt       => ScrodStatus.TbFifoCnt,
        tbfifo_err_cnt   => ScrodStatus.TbFifoFullCnt,
        qt_fifo_err_cnt  => ScrodStatus.QtFifoFullCnt,
        trg_cnt          => ScrodStatus.TrgCnt,
        full_proc_cnt    => ScrodStatus.FullProcCnt,
        simp_proc_cnt    => ScrodStatus.SimpProcCnt,
        null_proc_cnt    => ScrodStatus.NullProcCnt,
        -- occ_err_cnt      => ScrodStatus.HitsOverflowCnt,
        wave_stat        => ScrodStatus.WaveStat,
        debug_wave_we    => ScrodStatus.debug_wave_we,
        debug_wave_din   => ScrodStatus.debug_wave_din,
        SPS_hist_rd_data => ScrodStatus.SPS_hist_rd_data,
        -- debug
        -- ctime_max        => ScrodStatus.CTimeMax,
        
        -- pins to RAM
        RAM_IO           => RAM_IO,
        RAM_ADDR         => RAM_ADDR,
        RAM_WEb          => RAM_WEb,
        RAM_OEb          => RAM_OEb,
        
        -- bus A pins
        BUSA_WR_ADDRCLR  => BUSA_WR_ADDRCLR,
        BUSA_DO          => BUSA_DO,
        BUSA_RAMP        => BUSA_RAMP,
        BUSA_CLR         => BUSA_CLR,
        BUSA_RD_COLSEL   => BUSA_RD_COLSEL,
        BUSA_RD_ENA      => BUSA_RD_ENA,
        BUSA_RD_ROWSEL   => BUSA_RD_ROWSEL,
        BUSA_SAMPLESEL   => BUSA_SAMPLESEL,
        BUSA_SR_CLEAR    => BUSA_SR_CLEAR,
        BUSA_SR_SEL      => BUSA_SR_SEL,
        
        -- bus B pins
        BUSB_WR_ADDRCLR  => BUSB_WR_ADDRCLR,
        BUSB_DO          => BUSB_DO,
        BUSB_RAMP        => BUSB_RAMP,
        BUSB_CLR         => BUSB_CLR,
        BUSB_RD_COLSEL   => BUSB_RD_COLSEL,
        BUSB_RD_ENA      => BUSB_RD_ENA,
        BUSB_RD_ROWSEL   => BUSB_RD_ROWSEL,
        BUSB_SAMPLESEL   => BUSB_SAMPLESEL,
        BUSB_SR_CLEAR    => BUSB_SR_CLEAR,
        BUSB_SR_SEL      => BUSB_SR_SEL,
        
        -- daughter card pins
        WR1_ENA          => WR1_ENA,
        WR2_ENA          => WR2_ENA,
        SSTIN_N          => SSTIN_N,
        SSTIN_P          => SSTIN_P,
        -- TDC_DONE         => TDC_DONE,
        SAMPLESEL_ANY    => SAMPLESEL_ANY,
        SR_CLOCK         => SR_CLOCK,
        
        busy             => open
    );

        
        
    targetx_dac_control_i : entity work.targetx_dac_control
    port map(
        CLK           => clk,
        
        LOAD_PERIOD   => ScrodConfig.TxLoadPeriod,
        LATCH_PERIOD  => ScrodConfig.TxLatchPeriod,
        
        REG_DATA      => ScrodConfig.TxRegData,
        UPDATE        => ScrodControl.TxRegUpdate,
        
        busy          => ScrodStatus.TxRegBusy,
        
        SIN           => asic_sin,
        SCLK          => asic_sclk,
        PCLK          => asic_pclk
    );
        

    
    mppc_hv_dac_wrapper_i : entity work.mppc_dacs_wrapper_dac088s085
    port map(
        ------------CLOCK-----------------
        clk           => clk,
        ------------DAC PARAMETERS--------
        DAC_NUMBER    => ScrodConfig.MppcDacCtrl(15 downto 12),  -- Number,
        DAC_ADDR      => ScrodConfig.MppcDacCtrl(11 downto 8),  -- Addr,
        DAC_VALUE     => ScrodConfig.MppcDacCtrl(7 downto 0),  -- Value,
        
        WRITE_STROBE  => ScrodControl.MppcDacUpdate,
        busy          => ScrodStatus.MppcDacBusy,
        ------------HW INTERFACE----------
        SCK_DAC       => SCK_DAC,
        DIN_DAC       => DIN_DAC,
        TDC_CS_DAC    => TDC_CS_DAC
    );



    -- (CK) commented out module for timing closure (since it needs work anyway)
    -- check comments in Module_ADC_MCP3221_I2C_new for details
    -----------------------------------------------------------------
    -- mppc_current_measurement : entity work.Module_ADC_MCP3221_I2C_new
    -- port map(
    --    clock       => clk,
    --    reset       => ScrodControl.ADCReset,
    -- 
    --    debugmode   => ScrodConfig.ADCdebug,
    -- 
    --    sda         => i_sda_mon,
    --    scl         => i_scl_mon,
    -- 
    --    runADC      => ScrodControl.RunADC,
    --    ADCOutput   => ScrodStatus.MppcAdcData
    -- 
    -- );
    -- SDA_MON <= i_sda_mon ;
    -- SCL_MON <= i_scl_mon;
    ---------------------------------------------------------------



    -- #CK had warning HDLCompiler:946 b/c "c1 => not clk" in previous ODDR2 inst." 
    -- Decided to bring out inverted clock directly from pll_base located in b2tt_clk_s6.
    wilkinson_clock_generation : for i in 0 to 9 generate
       -- make 2x clk using OLOGIC2 resources
       clock_frequency_doubling : ODDR2 port map (
          Q => wilk_clk(i),
          C0 => clk,
          C1 => clkinv,
          CE => '1',
          D0 => '0',
          D1 => '1',
          R => '0',
          S => '0'
       );
       -- make differential output
       differential_output_buffer : OBUFDS port map (i => wilk_clk(i), o => WL_CLK_P(i), ob => WL_CLK_N(i));
    end generate;   
    -- Might be possible to get 4x wilk_clk by bringing 2x clk out of pll_base.
    -- Need to test and see what the TargetX and associated circuit can handle.
    


   
end Behavioral;