Belle II KLM Scint Firmware  1
klm_intfc.vhd
1 --*********************************************************************************
2 -- Indiana University
3 -- Center for Exploration of Energy and Matter (CEEM)
4 --
5 -- Project: Belle-II
6 --
7 -- Author: Brandon Kunkler
8 --
9 -- Date: 06/04/2014
10 --
11 --*********************************************************************************
12 -- Description:
13 --
14 -- Top level KLM SCROD design for Data Concentrator interface integration.
15 --
16 -- There are four data streams:
17 -- 1) Trigger data stream. The TARGET trigger bits are connected directly to and
18 -- processed by the conc_intfc.
19 -- 2) The DAQ data stream. This is an entire triggers worth of DAQ data that will
20 -- be forwarded to the COPPER. As of creation the DAQ data stream from each
21 -- TARGET must be combined before transmitting to the conc_intfc. The DAQ data
22 -- format was not known at time of creation. Connecting all TARGETs to the
23 -- conc_intfc and combing there would be more consistent. The con_intfc
24 -- inserts the lowest 16-bits of the trigger tag to be used for combing scint
25 -- and RPC data.
26 -- 3) Status data stream. All status registers will be forward to the Data Concentrator
27 -- every so many DAQ packets (trigger cycles).
28 -- 4) Control data stream. The Data Concentrator will transmit a single (large) packet
29 -- containing all run control values as specified in the interface document.
30 --
31 -- B2TT Modifications:
32 -- 1) Add dblclock to b2tt_clk_s6.
33 --
34 -- NOTE:
35 -- 1) The delay (in clocks) between b2tt runreset and the TDC counter sync must be
36 -- known (controlled) to keep scint and RPC TDCs in phase.
37 -- 2) MAXDELAY constraints may need to be placed on the b2tt runreset signal shift
38 -- register in the timing_ctrl entity to distribute the FFs across the chip.
39 -- 3) The asynchronous nature of tx_dst_rdy_n may cause issues in the conc_intfc
40 -- state machine.
41 -- 4) The Aurora core is modified; the files in the ipore directory are not used
42 -- during implementation.
43 -- 5) Search on --? or --! for other important notes.
44 --
45 -- Issues:
46 -- 1) Will only work when the FTSW clock is used for both the MGT and
47 -- TXUSERCLK/TXUSERCLK2 (the onboard oscillator cannot be used). The GTPOUTCLK
48 -- will need to be used for all Aurora logic to use oscillator - requires clock
49 -- domain crossing.
50 -- 2. line 451: exttb <= target_tb_i; -- FIXME
51 -- Not sure what is up with "FIXME."
52 -- This assignment explains all the warnings about ext_tb_format
53 --*********************************************************************************
54 library ieee;
55  use ieee.std_logic_1164.all;
56  use ieee.numeric_std.all;
57  use ieee.std_logic_unsigned.all;
58  use ieee.std_logic_misc.all;
59 library work;
60  use work.time_order_pkg.all;
61  use work.tdc_pkg.all;
62  use work.conc_intfc_pkg.all;
63  use work.klm_scrod_pkg.all;
64 -- synthesis translate_off
65 library unisim;
66  use unisim.vcomponents.all;
67 -- synthesis translate_on
68 
69 entity klm_intfc is
70 generic(
71  NUM_GTS : integer := 1;
72  REVISION : string := "A5"; --A2,A3,A4,A5
73  CLKSRC : string := "FTSW";--FTSW, OBOSC
74  AURORA_CC_USE : boolean := FALSE;
75  LINK_TEST : std_logic := '0';
76  TB_PERIOD : std_logic_vector(15 downto 0) := X"2112";
77  DAQ_GEN_SIM_SPEEDUP : std_logic := '0';
78  SIM_REFSELDYPLL : bit_vector(2 downto 0) := "000";
79  USE_4NS_TDC_CLK : std_logic := '0');
80 port(
81  sysclk : in std_logic;
82  sysclk2x : in std_logic;
83 
84  -- B2TT signals
85  b2tt_b2clkup : in std_logic;
86  -- b2tt_b2ttup : in std_logic;
87  -- b2tt_trgout : in std_logic;
88  -- b2tt_b2plllk : out std_logic; --aurora_stat.gtlock
89  b2tt_ctime : in std_logic_vector(26 downto 0);
90  b2tt_divclk1 : in std_logic_vector(1 downto 0);
91  b2tt_divclk2 : in std_logic_vector(1 downto 0);
92  b2tt_runreset : in std_logic;
93  -- b2tt_feereset : in std_logic;
94  b2tt_gtpreset : in std_logic;
95  b2tt_b2linkwe : out std_logic;
96  -- b2tt_b2lreset : in std_logic;
97  b2tt_fifordy : in std_logic;
98  b2tt_fifodata : in std_logic_vector(95 downto 0);
99  b2tt_fifonext : out std_logic;
100  b2tt_frame : in std_logic;
101  b2tt_trgtag : in std_logic_vector(31 downto 0);
102 
103  -- ASIC Interface
104  target_tb : in tb_vec_type;
105 
106  -- SFP interface
107  mgttxfault : in std_logic_vector(1 to NUM_GTS);
108  mgtmod0 : in std_logic_vector(1 to NUM_GTS);
109  mgtlos : in std_logic_vector(1 to NUM_GTS);
110  mgttxdis : out std_logic_vector(1 to NUM_GTS);
111  mgtmod2 : out std_logic_vector(1 to NUM_GTS);
112  mgtmod1 : out std_logic_vector(1 to NUM_GTS);
113  mgtclk0p : in std_logic;
114  mgtclk0n : in std_logic;
115  mgtclk1p : in std_logic;
116  mgtclk1n : in std_logic;
117  mgtrxp : in std_logic;
118  mgtrxn : in std_logic;
119  mgttxp : out std_logic;
120  mgttxn : out std_logic;
121  sfp_stat : out SFP_Status_t;
122  aurora_stat : out Aurora_Status_t;
123  -- Run control local link output
124  -- rcl_dst_rdy_n : in std_logic;
125  -- rcl_sof_n : out std_logic;
126  -- rcl_eof_n : out std_logic;
127  rcl_src_rdy_n : out std_logic;
128  rcl_data : out std_logic_vector(15 downto 0);
129 
130  qt_fifo_rd_en : out std_logic;
131  qt_fifo_rd_d : in std_logic_vector(17 downto 0);
132  qt_fifo_empty : in std_logic;
133  qt_fifo_evt_rdy : in std_logic;
134 
135 
136  exttb : out tb_vec_type; --re-timed trigger bits for ASIC read
137  trgon : in std_logic;
138 
139  klm_status_upd : in std_logic;
140  stat_tx_in_progress : out std_logic;
141  klm_status_regs : in stat_reg_type );
142 end klm_intfc;
143 
144 --- architecture -------------------------------------------------------
145 architecture behave of klm_intfc is
146 
147  component IBUFDS is
148  generic(
149  DIFF_TERM : boolean := TRUE; -- Differential Termination
150  IBUF_LOW_PWR : boolean := FALSE; -- Low power (TRUE) vs. performance (FALSE) setting for referenced I/O standards
151  IOSTANDARD : string := "DEFAULT");
152  port(
153  O : out std_logic;-- Buffer output
154  I : in std_logic; -- Diff_p buffer input (connect directly to top-level port)
155  IB : in std_logic);-- Diff_n buffer input (connect directly to top-level port)
156  end component;
157 
158  component IBUF is
159  port(
160  O : out std_logic; -- buffer output
161  I : in std_logic); -- buffer input (connect directly to top-level port)
162  end component;
163 
164  component OBUF is
165  port(
166  O : out std_logic; -- buffer output
167  I : in std_logic); -- buffer input (connect directly to top-level port)
168  end component;
169 
170  component timing_ctrl is
171  port(
172  clk : in std_logic;
173  clk2x : in std_logic;
174  tdc_sync : in std_logic;
175  runreset : in std_logic;
176  tdcrst : out std_logic_vector(1 to 3);--vector so we can distribute to meet timing
177  tdcce_2x : out std_logic_vector(1 to 5)); -- _Nx is N times clock period
178  end component;
179 
180  component klm_aurora_intfc is
181  generic(
182  SIM_GTPRESET_SPEEDUP : integer;
183  CLK_CORRECT_USE : boolean);
184  port(
185  refseldypll : in std_logic_vector(2 downto 0);
186  ref_clk0 : in std_logic;
187  ref_clk1 : in std_logic;
188  user_clk : in std_logic;
189  sync_clk : in std_logic;
190  reset : in std_logic;
191  gt_reset : in std_logic;
192  plllock : in std_logic;
193  -- LocalLink TX Interface
194  tx_dst_rdy_n : out std_logic;
195  tx_src_rdy_n : in std_logic;
196  tx_sof_n : in std_logic;
197  tx_eof_n : in std_logic;
198  tx_d : in std_logic_vector(0 to 15);
199  tx_rem : in std_logic;
200  -- LocalLink RX Interface
201  rx_src_rdy_n : out std_logic;
202  rx_sof_n : out std_logic;
203  rx_eof_n : out std_logic;
204  rx_rem : out std_logic;
205  rx_d : out std_logic_vector(0 to 15);
206  -- Status
207  gtlock : out std_logic;
208  hard_err : out std_logic;
209  soft_err : out std_logic;
210  frame_err : out std_logic;
211  channel_up : out std_logic;
212  lane_up : out std_logic;
213  warn_cc : out std_logic;
214  do_cc : out std_logic;
215  -- Control
216  powerdown : in std_logic;
217  loopback : in std_logic_vector(2 downto 0);
218  -- GT I/O
219  rxp : in std_logic;
220  rxn : in std_logic;
221  txp : out std_logic;
222  txn : out std_logic);
223  end component;
224 
225  component conc_intfc is
226  generic(
227  USE_4NS_TDC_CLK : std_logic := '0');
228  port(
229  -- inputs ---------------------------------------------
230  sys_clk : in std_logic;
231  tdc_clk : in std_logic;
232  ce : in std_logic_vector(1 to 5);
233  --B2TT interface
234  b2tt_runreset : in std_logic;
235  b2tt_runreset_tdc : in std_logic_vector(1 to 3);
236  b2tt_gtpreset : in std_logic;
237  b2tt_frame2x : in std_logic;
238  b2tt_fifordy : in std_logic;
239  b2tt_fifodata : in std_logic_vector (95 downto 0);
240  b2tt_fifonext : out std_logic;
241  --TARGET ASIC trigger interface (trigger bits)
242  target_tb : in tb_vec_type;
243  -- target_tb16 : in std_logic_vector(1 to TDC_NASICS);
244  -- status sent to concentrator
245  status_upd : in std_logic;
246  stat_tx_in_progress : out std_logic;
247  status_regs : in stat_reg_type;
248  -- Aurora local input local link (from Concentrator)
249  -- rx_dst_rdy_n : out std_logic;
250  -- rx_sof_n : in std_logic;
251  -- rx_eof_n : in std_logic;
252  rx_src_rdy_n : in std_logic;
253  rx_data : in std_logic_vector(15 downto 0);
254  -- DAQ data local link input (TARGET DAQ data when triggered)
255  daq_dst_rdy_n : out std_logic;
256  daq_sof_n : in std_logic;--start of trigger
257  daq_eof_n : in std_logic;--end of trigger
258  daq_src_rdy_n : in std_logic;
259  daq_data : in std_logic_vector(15 downto 0);
260  -- outputs --------------------------------------------
261  exttrg : out std_logic;
262  exttb : out tb_vec_type;
263  -- Aurora local ouptput local link (to Concentrator)
264  tx_dst_rdy_n : in std_logic;
265  tx_sof_n : out std_logic;
266  tx_eof_n : out std_logic;
267  tx_src_rdy_n : out std_logic;
268  tx_data : out std_logic_vector(15 downto 0);
269 
270  -- Run control local link output
271  -- rcl_dst_rdy_n : in std_logic;
272  -- rcl_sof_n : out std_logic;
273  -- rcl_eof_n : out std_logic;
274  rcl_src_rdy_n : out std_logic;
275  rcl_data : out std_logic_vector(15 downto 0));
276  end component;
277 
278 
279  component sfp_stat_ctrl is
280  generic(
281  NUM_GTS : integer);
282  port(
283  clk : in std_logic;
284  txfault : in std_logic_vector(1 to NUM_GTS);
285  txdis : out std_logic_vector(1 to NUM_GTS);
286  mod2 : out std_logic_vector(1 to NUM_GTS);
287  mod1 : out std_logic_vector(1 to NUM_GTS);
288  mod0 : in std_logic_vector(1 to NUM_GTS);
289  los : in std_logic_vector(1 to NUM_GTS);
290  fault_flag : out std_logic;
291  mod_flag : out std_logic;
292  los_flag : out std_logic);
293  end component;
294 
295  alias NUM_ASICS is TDC_NASICS;
296 
297  constant NUM_ATBS : integer := 5; --ASIC trigger bits
298 
299  constant REFCLKSEL : std_logic_vector(2 downto 0) := "000";
300 
301  signal mgtclk0_i : std_logic;
302  signal mgtclk1_i : std_logic;
303  signal mgtrxp_i : std_logic;
304  signal mgtrxn_i : std_logic;
305  signal mgttxp_i : std_logic;
306  signal mgttxn_i : std_logic;
307  signal mgttxfault_i : std_logic_vector(1 to NUM_GTS);
308  signal mgtmod0_i : std_logic_vector(1 to NUM_GTS);
309  signal mgtlos_i : std_logic_vector(1 to NUM_GTS);
310 
311  signal mgttxdis_i : std_logic_vector(1 to NUM_GTS);
312  signal mgtmod2_i : std_logic_vector(1 to NUM_GTS);
313  signal mgtmod1_i : std_logic_vector(1 to NUM_GTS);
314 
315  signal target_tb_i : tb_vec_type;
316  -- signal target_tb16_i : std_logic_vector(1 to TDC_NASICS) := (others => '0');
317 
318  signal control_fake_i : std_logic := '0';
319  signal status_fake_i : std_logic := '0';
320 
321  signal sys_clk_ib : std_logic;
322  signal sys_clk2x_ib : std_logic;
323 
324  signal mgttxfault_qi : std_logic_vector(1 to NUM_GTS);
325  signal mgtmod0_qi : std_logic_vector(1 to NUM_GTS);
326  signal mgtlos_qi : std_logic_vector(1 to NUM_GTS);
327 
328  signal mgttxdis_iq : std_logic_vector(1 to NUM_GTS);
329  signal mgtmod2_iq : std_logic_vector(1 to NUM_GTS);
330  signal mgtmod1_iq : std_logic_vector(1 to NUM_GTS);
331 
332  -- B2TT Signals
333  signal b2tt_b2clkup_i : std_logic;
334  -- signal b2tt_b2ttup_i : std_logic;
335  -- signal b2tt_trgout_i : std_logic;
336  signal b2tt_ctime_i : std_logic_vector(26 downto 0);
337  signal b2tt_divclk1_i : std_logic_vector(1 downto 0);
338  signal b2tt_divclk2_i : std_logic_vector(1 downto 0);
339  signal b2tt_runreset_i : std_logic;
340  -- signal b2tt_feereset_i : std_logic;
341  signal b2tt_gtpreset_i : std_logic;
342  -- signal b2tt_b2lreset_i : std_logic;
343  signal b2tt_b2ttver_i : std_logic_vector(15 downto 0);
344  signal b2tt_fifordy_i : std_logic;
345  signal b2tt_fifodata_i : std_logic_vector(95 downto 0);
346  signal b2tt_exprun_i : std_logic_vector(31 downto 0);
347  signal b2tt_frame_i : std_logic;
348  signal b2tt_frame9_i : std_logic;
349  signal b2tt_trgtag_i : std_logic_vector(31 downto 0);
350  signal b2tt_fifonext_i : std_logic;
351 
352  signal b2tt_ctime_or : std_logic;
353 
354  -- signal rx_dst_rdy_n : std_logic;
355  -- signal rx_sof_n : std_logic;
356  -- signal rx_eof_n : std_logic;
357  signal rx_src_rdy_n : std_logic;
358  signal rx_data : std_logic_vector(15 downto 0);
359 
360  signal tx_dst_rdy_n : std_logic;
361  signal tx_sof_n : std_logic;
362  signal tx_eof_n : std_logic;
363  signal tx_src_rdy_n : std_logic;
364  signal tx_data : std_logic_vector(15 downto 0);
365 
366  signal tdc_clk : std_logic;
367  signal tdc_ce : std_logic_vector(1 to 5);
368  signal b2tt_frame2x : std_logic_vector(1 to 3);
369  signal b2tt_runreset2x : std_logic_vector(1 to 3);
370  signal b2tt_runreset_tdc : std_logic_vector(1 to 3);
371 
372  signal status_regs : stat_reg_type;
373  signal ctrl_regs : ctrl_reg_type;
374  signal daq_dst_rdy_n : std_logic;
375  signal daq_sof_n : std_logic;
376  signal daq_eof_n : std_logic;
377  signal daq_src_rdy_n : std_logic;
378  signal daq_data : std_logic_vector(15 downto 0);
379  signal inttb : tb_vec_type;
380 
381 
382  attribute keep : string;
383  -- attribute keep of b2tt_runreset2x : signal is "true"; -- WHY? does not have a driver. CK.
384  attribute keep of b2tt_trgtag_i : signal is "true";
385 
386 
387 begin
388 
389  sys_clk_ib <= sysclk;
390  sys_clk2x_ib <= sysclk2x;
391 
392  process(sysclk)
393  begin
394  if rising_edge(sysclk) then
395  b2tt_b2clkup_i <= b2tt_b2clkup;
396  -- b2tt_b2ttup_i <= b2tt_b2ttup;
397  -- b2tt_trgout_i <= b2tt_trgout;
398  b2tt_ctime_i <= b2tt_ctime;
399  -- b2tt_feereset_i <= b2tt_feereset;
400  b2tt_gtpreset_i <= b2tt_gtpreset;
401  -- b2tt_b2lreset_i <= b2tt_b2lreset;
402  b2tt_fifordy_i <= b2tt_fifordy;
403  b2tt_fifodata_i <= b2tt_fifodata;
404  b2tt_frame_i <= b2tt_frame;
405  b2tt_trgtag_i <= b2tt_trgtag;
406  b2tt_runreset_i <= b2tt_runreset;
407 
408  b2tt_fifonext <= b2tt_fifonext_i;
409  end if;
410  end process;
411 
412 
413  -------------------------------------------------
414  -- Input Buffers
415  -------------------------------------------------
416  mgtclk0_inst : IBUFDS
417  port map (
418  O => mgtclk0_i,-- Buffer output
419  I => mgtclk0p, -- Diff_p buffer input (connect directly to top-level port)
420  IB => mgtclk0n -- Diff_n buffer input (connect directly to top-level port)
421  );
422 
423  mgtclk1_inst : IBUFDS
424  port map (
425  O => mgtclk1_i,-- Buffer output
426  I => mgtclk1p, -- Diff_p buffer input (connect directly to top-level port)
427  IB => mgtclk1n -- Diff_n buffer input (connect directly to top-level port)
428  );
429 
430  asic_IBUF_GEN :
431  for I in 1 to 10 generate
432  atb_IBUF_GEN :
433  for J in 5 downto 1 generate
434  atb_IBUF : IBUF
435  port map(
436  O => target_tb_i(I)(J),
437  I => target_tb(I)(J)
438  );
439  end generate;
440  end generate;
441 
442  exttb <= target_tb_i; -- FIXME
443 
444  mgttxfault_IBUF_GEN :
445  for I in 1 to NUM_GTS generate
446  mgttxfault_IBUF : IBUF
447  port map(
448  O => mgttxfault_i(I),
449  I => mgttxfault(I)
450  );
451  end generate;
452 
453  mgtmod0_IBUF_GEN :
454  for I in 1 to NUM_GTS generate
455  mgtmod0_IBUF : IBUF
456  port map(
457  O => mgtmod0_i(I),
458  I => mgtmod0(I)
459  );
460  end generate;
461 
462  mgtlos_IBUF_GEN :
463  for I in 1 to NUM_GTS generate
464  mgtlos_IBUF : IBUF
465  port map(
466  O => mgtlos_i(I),
467  I => mgtlos(I)
468  );
469  end generate;
470 
471  mgtrxp_IBUF : IBUF
472  port map(
473  O => mgtrxp_i,
474  I => mgtrxp
475  );
476 
477  mgtrxn_IBUF : IBUF
478  port map(
479  O => mgtrxn_i,
480  I => mgtrxn
481  );
482 
483  -------------------------------------------------
484  -- Output Buffers
485  -------------------------------------------------
486  mgttxdis_OBUF_GEN :
487  for I in 1 to NUM_GTS generate
488  mgttxdis_OBUF : OBUF
489  port map(
490  O => mgttxdis(I),
491  I => mgttxdis_iq(I)
492  );
493  end generate;
494 
495  mgtmod2_OBUF_GEN :
496  for I in 1 to NUM_GTS generate
497  mgtmod2_OBUF : OBUF
498  port map(
499  O => mgtmod2(I),
500  I => mgtmod2_iq(I)
501  );
502  end generate;
503 
504  mgtmod1_OBUF_GEN :
505  for I in 1 to NUM_GTS generate
506  mgtmod1_OBUF : OBUF
507  port map(
508  O => mgtmod1(I),
509  I => mgtmod1_iq(I)
510  );
511  end generate;
512 
513  mgttxp_OBUF : OBUF
514  port map(
515  O => mgttxp,
516  I => mgttxp_i
517  );
518 
519  mgttxn_OBUF : OBUF
520  port map(
521  O => mgttxn,
522  I => mgttxn_i
523  );
524 
525 
526  ----------------------------------------------------------------
527  -- Clock enables, resets, strobes, etc.
528  ----------------------------------------------------------------
529  tmg_ctrl_ins : timing_ctrl
530  port map(
531  clk => sys_clk_ib,
532  clk2x => sys_clk2x_ib,
533  tdc_sync => b2tt_frame_i, --tdc_sync,--!
534  runreset => b2tt_runreset_i,
535  tdcrst => b2tt_frame2x,
536  tdcce_2x => tdc_ce
537  );
538 
539  fast_tdc_clk: if USE_4NS_TDC_CLK = '1' generate
540  tdc_clk <= sys_clk2x_ib;
541  b2tt_runreset_tdc <= b2tt_runreset2x;
542  end generate;
543 
544  reg_tdc_clk: if USE_4NS_TDC_CLK = '0' generate
545  tdc_clk <= sys_clk_ib;
546  b2tt_runreset_tdc <= (others => b2tt_runreset_i);
547  end generate;
548 
549  ----------------------------------------------------------------
550  -- Aurora Core.
551  ----------------------------------------------------------------
552  aurora_ins : klm_aurora_intfc
553  generic map(
554  SIM_GTPRESET_SPEEDUP => 1,
555  CLK_CORRECT_USE => AURORA_CC_USE)
556  port map(
557  refseldypll => refclksel,
558  ref_clk0 => mgtclk0_i,
559  ref_clk1 => mgtclk1_i,
560  user_clk => sys_clk_ib,
561  sync_clk => sys_clk2x_ib,
562  reset => b2tt_runreset_i, --b2tt_b2lreset,
563  gt_reset => b2tt_runreset_i, --b2tt_gtpreset,--
564  plllock => b2tt_b2clkup_i, --b2tt_b2plllk,
565  -- LocalLink TX Interface
566  tx_dst_rdy_n => tx_dst_rdy_n,
567  tx_src_rdy_n => tx_src_rdy_n,
568  tx_sof_n => tx_sof_n,
569  tx_eof_n => tx_eof_n,
570  tx_d => tx_data,
571  tx_rem => '1', --?
572  -- LocalLink RX Interface
573  rx_src_rdy_n => rx_src_rdy_n,
574  rx_sof_n => open, --rx_sof_n, (CK)
575  rx_eof_n => open, --rx_eof_n, (CK)
576  rx_rem => open, --?
577  rx_d => rx_data,
578  -- Status
579  gtlock => aurora_stat.gtlock,
580  hard_err => aurora_stat.hard_err,
581  soft_err => aurora_stat.soft_err,
582  frame_err => aurora_stat.frame_err,
583  channel_up => aurora_stat.channel_up,
584  lane_up => aurora_stat.lane_up,
585  warn_cc => aurora_stat.warn_cc, -- the may help in conc interface
586  do_cc => aurora_stat.do_cc,
587  -- Control
588  powerdown => '0',
589  loopback => "000",
590  -- GT I/O
591  rxp => mgtrxp_i,
592  rxn => mgtrxn_i,
593  txp => mgttxp_i,
594  txn => mgttxn_i
595  );
596 
597  ----------------------------------------------------------------
598  -- Data Concentrator interface. Generate and time-order TDC.
599  -- Combine trigger, DAQ, and status data. Receive control data.
600  ----------------------------------------------------------------
601  conc_intfc_ins : conc_intfc
602  generic map (
603  USE_4NS_TDC_CLK => USE_4NS_TDC_CLK
604  )
605  port map(
606  -- inputs ---------------------------------------------
607  sys_clk => sys_clk_ib,
608  tdc_clk => tdc_clk,
609  ce => tdc_ce,
610  --B2TT interface
611  b2tt_runreset => b2tt_runreset_i,
612  b2tt_runreset_tdc => b2tt_runreset_tdc,
613  b2tt_frame2x => b2tt_frame2x(1),
614  b2tt_gtpreset => b2tt_gtpreset_i,
615  b2tt_fifordy => b2tt_fifordy_i ,
616  b2tt_fifodata => b2tt_fifodata_i,
617  b2tt_fifonext => b2tt_fifonext_i,
618  --TARGET ASIC trigger interface (trigger bits)
619  target_tb => inttb,
620  -- target_tb16 => target_tb16_i,
621  -- status sent to concentrator
622  status_upd => klm_status_upd,
623  stat_tx_in_progress => stat_tx_in_progress,
624  status_regs => status_regs,
625  -- Aurora local input local link (from Concentrator)
626  -- rx_dst_rdy_n => rx_dst_rdy_n,
627  -- rx_sof_n => rx_sof_n,
628  -- rx_eof_n => rx_eof_n,
629  rx_src_rdy_n => rx_src_rdy_n,
630  rx_data => rx_data,
631  -- DAQ data local link input (TARGET DAQ data when triggered)
632  daq_dst_rdy_n => daq_dst_rdy_n,
633  daq_sof_n => daq_sof_n,--start of trigger
634  daq_eof_n => daq_eof_n,--end of trigger
635  daq_src_rdy_n => daq_src_rdy_n,
636  daq_data => daq_data,
637  -- outputs --------------------------------------------
638  exttrg => open,
639  exttb => open,
640  -- Aurora local ouptput local link (to Concentrator)
641  tx_dst_rdy_n => tx_dst_rdy_n,
642  tx_sof_n => tx_sof_n,
643  tx_eof_n => tx_eof_n,
644  tx_src_rdy_n => tx_src_rdy_n,
645  tx_data => tx_data,
646  -- Run control local link output
647  -- rcl_dst_rdy_n => rcl_dst_rdy_n,
648  -- rcl_sof_n => rcl_sof_n,
649  -- rcl_eof_n => rcl_eof_n,
650  rcl_src_rdy_n => rcl_src_rdy_n,
651  rcl_data => rcl_data
652  );
653 
654  ----------------------------------------------------------------
655  -- Create a single DAQ data stream from all ASICs.
658  -- VS: TODO move this entity to the top level
659  -- VS: There is something wrong with fifonext signal. FIXME
660  ----------------------------------------------------------------
661  daq_gen_ins : entity work.daq_gen_readout
662  port map(
663  clk => sys_clk_ib,
664  reset => b2tt_runreset_i,
665 
666  tx_dst_rdy_n => daq_dst_rdy_n,
667  tx_src_rdy_n => daq_src_rdy_n,
668  tx_sof_n => daq_sof_n,
669  tx_eof_n => daq_eof_n,
670  tx_d => daq_data,
671 
672  qt_fifo_rd_en => qt_fifo_rd_en,
673  qt_fifo_rd_d => qt_fifo_rd_d,
674  qt_fifo_empty => qt_fifo_empty,
675  qt_fifo_evt_rdy => qt_fifo_evt_rdy
676  );
677 
678  inttb <= target_tb_i when trgon = '1' else (others => (others => '0'));
679 
680  ----------------------------------------------------------------
681  -- Deal with the SFP connections. // VS: do we need this?
682  ----------------------------------------------------------------
683  sfp_stat_ctrl_ins : sfp_stat_ctrl
684  generic map(
685  NUM_GTS => NUM_GTS)
686  port map(
687  clk => sys_clk_ib,
688  txfault => mgttxfault_qi,
689  txdis => mgttxdis_i,
690  mod2 => mgtmod2_i,
691  mod1 => mgtmod1_i,
692  mod0 => mgtmod0_qi,
693  los => mgtlos_qi,
694  fault_flag => sfp_stat.fault_flag,
695  mod_flag => sfp_stat.mod_flag,
696  los_flag => sfp_stat.los_flag
697  );
698 
699 ---------------------------------------------------------------------
700 -- Concurrent statements
701 ---------------------------------------------------------------------
702 
703  --------------------------------------
704  -- Map the status registers
705  --------------------------------------
706  STAT_GEN : for I in 0 to NUM_SCROD_REGS-1 generate
707  status_regs(I) <= klm_status_regs(I);
708  end generate;
709 
710 
711  b2tt_b2linkwe <= (not tx_src_rdy_n);
712 
713 ---------------------------------------------------------------------
714 -- Synchronous processes
715 ---------------------------------------------------------------------
716 ----------------------------------------------------------------
717 -- Input registers to be placed in the I/O ring
718 ----------------------------------------------------------------
719 
720  --------------------------------------
721  -- System clock domain input registers
722  --------------------------------------
723  sysin_regs : process(sys_clk_ib)
724  begin
725  if (sys_clk_ib'event and sys_clk_ib = '1') then
726  mgttxfault_qi <= mgttxfault_i;
727  mgtmod0_qi <= mgtmod0_i;
728  mgtlos_qi <= mgtlos_i;
729  end if;
730  end process;
731 
732 ----------------------------------------------------------------
733 -- Output registers to be placed in the I/O ring
734 ----------------------------------------------------------------
735 
736  --------------------------------------
737  -- System clock domain output registers
738  --------------------------------------
739  sout_regs : process(sys_clk_ib)
740  begin
741  if (sys_clk_ib'event and sys_clk_ib = '1') then
742  mgttxdis_iq <= mgttxdis_i;
743  mgtmod2_iq <= mgtmod2_i;
744  mgtmod1_iq <= mgtmod1_i;
745  end if;
746  end process;
747 
748 end behave;
conc_intfc_pkg
Definition: conc_intfc_pkg.vhd:24
daq_gen_readout
Definition: daq_gen_readout.vhd:6
klm_intfc
Definition: klm_intfc.vhd:69
sfp_stat_ctrl
Definition: sfp_stat_ctrl.vhd:22
conc_intfc
Definition: conc_intfc.vhd:42
klm_scrod_pkg
Definition: klm_scrod_pkg.vhd:22
klm_aurora_intfc
Definition: klm_aurora_intfc.vhd:23
timing_ctrl
Definition: timing_ctrl.vhd:22