1 --********************************************************************************* 2 -- Indiana University CEEM 4 -- Author: Brandon Kunkler 6 --********************************************************************************* 9 -- Reads trigger and DAQ packets from the scintillator electronics. The trigger 10 -- packets are comprised of of many smaller raw samples. Trigger raw samples are 11 -- channel and time. DAQ packets are an entire triggers worth of data. Data bandwith 12 -- is increased by not using the overhead of marking each raw sample on the link. 13 -- A pause should be inserted after the sof_n signal is asserted and ~4 pauses should 14 -- be inserted after eof_n is asserted. 16 -- ##### Deficiencies/Issues 17 -- 1. Will drop a word if a clock correction sequence occurs during the middle of 18 -- a packet. Need to re-transmit if tx_dst_rdy_n is asserted while tx_src_rdy_n 19 -- is asserted. Could tranistion to a wait state that keeps all local link signals 20 -- the same until tx_dst_rdy_n is de-asserted. Or, could use the do_cc and warn_cc 21 -- signals to prevent sending data when tx_dst_rdy_n is going to be asserted. 22 -- 2. Does nothing with run control registers (may not matter). 23 -- 3. Does nothing with status registers. 24 -- 4. Need to add assertions to make sure no FIFO read or write errors occur. 25 -- 5. WARNING:HDLCompiler:746 - "/home/cketter/klm/firmware/klm_scrod/conc_intfc/source/conc_intfc.vhd" 26 -- Line 460: Range is empty (null range) --- trg_valid <= trg_fifo_re & trg_valid(trg_valid'length-1 downto 1); 27 -- I'm surprised this is not an error. 28 -- Need to evaluate importance of this signal and underlying logic. Seems to affect 29 -- trig Start-Of-Frame and End-Of-Frame sent to DC. (CK) 31 --********************************************************************************* 33 use ieee.std_logic_1164.
all;
34 use ieee.std_logic_unsigned.
all;
35 use ieee.numeric_std.
all;
36 use ieee.std_logic_misc.
all;
38 use work.time_order_pkg.
all;
44 USE_4NS_TDC_CLK : := '0' 47 -- inputs --------------------------------------------- 53 b2tt_runreset_tdc : in (1 to 3);
57 b2tt_fifodata : in (95 downto 0);
59 --TARGET ASIC trigger interface (trigger bits) 60 target_tb : in tb_vec_type;
61 -- target_tb16 : in std_logic_vector(1 to TDC_NASICS); 62 -- status sent to concentrator 64 stat_tx_in_progress : out ;
65 status_regs : in stat_reg_type;
66 -- Aurora local input local link (from Concentrator) 67 -- rx_dst_rdy_n : out std_logic; 68 -- rx_sof_n : in std_logic; 69 -- rx_eof_n : in std_logic; 71 rx_data : in (15 downto 0);
72 -- DAQ data local link input (TARGET DAQ data when triggered) 74 daq_sof_n : in ;
--start of trigger 75 daq_eof_n : in ;
--end of trigger 77 daq_data : in (15 downto 0);
78 -- outputs -------------------------------------------- 80 exttb : out tb_vec_type;
81 -- Aurora local ouptput local link (to Concentrator) 86 tx_data : out (15 downto 0);
87 -- Run control local link output 88 -- rcl_dst_rdy_n : in std_logic; 89 -- rcl_sof_n : out std_logic := '1'; 90 -- rcl_eof_n : out std_logic := '1'; 91 rcl_src_rdy_n : out := '1';
92 rcl_data : out (15 downto 0));
99 -- Inputs ----------------------------- 105 -- tb16 : in std_logic_vector(1 to TDC_NASICS); 106 fifo_re :
in (
1 to TDC_NASICS);
107 exttb_format :
in (
3 downto 0);
108 -- Outputs ----------------------------- 109 exttb :
out tb_vec_type;
110 fifo_ept :
out (
1 to TDC_NASICS);
111 tdc_dout :
out tdc_dout_type);
114 component time_order
is 120 src_epty :
in (
1 to TO_NUM_LANES);
121 din :
in tdc_dout_type;
122 src_re :
out (
1 to TO_NUM_LANES);
124 dout :
out (TO_WIDTH
-1 downto 0));
129 NUM_CHAN : ;
-- ASIC channels 130 LANEIW : ;
-- Lane in width 131 CHANIW : ;
-- Channel in width 132 CHANOW : ;
-- Channel out width 133 AXIS_VAL : );
-- Axis bit default 135 -- inputs --------------------------------------------- 138 lane :
in (LANEIW
-1 downto 0);
139 chan :
in (CHANIW
-1 downto 0);
142 trig_chan :
out (CHANOW
-1 downto 0));
150 din :
in (
17 downto 0);
153 dout :
out (
17 downto 0);
157 almost_empty :
out );
164 din :
in (
17 downto 0);
167 dout :
out (
17 downto 0);
171 almost_empty :
out );
174 type tx_fsm_type is ( 185 type word_shift_type is array ( range <> ) of (15 downto 0);
187 signal exttrg_ctr : (3 downto 0) := (others => '0');
189 signal tdc_rden : (1 to TDC_NASICS);
190 signal tdc_epty : (1 to TDC_NASICS);
191 signal tdc_dout : tdc_dout_type;
194 signal to_dout : (TO_WIDTH-1 downto 0);
195 signal to_valid : (1 downto 0);
197 signal trg_fifo_we : := '0';
198 signal trg_fifo_di : (17 downto 0);
199 signal trg_fifo_re : ;
200 signal trg_fifo_do : (17 downto 0);
201 signal trg_fifo_afull : ;
202 signal trg_fifo_epty : ;
203 signal trg_fifo_aepty : ;
204 signal trg_fifo_full : ;
205 -- signal trg_fifo_rderr : std_logic; 206 -- signal trg_fifo_wrerr : std_logic; 208 signal daq_fifo_we : := '0';
209 signal daq_fifo_di : (17 downto 0);
210 signal daq_fifo_re : ;
211 signal daq_fifo_do : (17 downto 0);
212 signal daq_fifo_afull : ;
213 signal daq_fifo_epty : ;
214 signal daq_fifo_aepty : ;
215 signal daq_fifo_full : ;
216 -- signal daq_fifo_rderr : std_logic; 217 -- signal daq_fifo_wrerr : std_logic; 220 signal trg_ch : (7 downto 0);
221 signal trg_ch_valid : ;
223 signal trg_valid : (0 downto 0);
224 signal trgsof_ctr : (7 downto 0);
225 signal trgeof_ctr : (7 downto 0);
231 signal daq_sof_q : (1 downto 0);
232 signal daq_eof_q : (1 downto 0);
233 signal daq_src_rdy_q : (1 downto 0);
234 signal daq_data_q : word_shift_type(1 downto 0);
235 signal daq_valid : (2 downto 0);
236 signal daq_di_addr : (2 downto 0);
237 signal daq_pause : (3 downto 0);
238 signal sts_pause : (1 downto 0);
239 signal idl_pause : (1 downto 0);
242 -- pakcet type counter (time spent writing trigger data) - just change the width to adjust 243 signal pkttp_ctr_ld : ;
244 signal pkttp_ctr_tc : ;
245 signal pkttp_ctr : (PKTTP_CTRW-1 downto 0);
246 signal trgpkt_ctr_ld : ;
247 signal trgpkt_ctr_en : ;
248 signal trgpkt_ctr_tc : ;
249 signal trgpkt_ctr : (TGPKT_CTRW-1 downto 0);
250 signal stspkt_ctr_ld : ;
251 signal stspkt_ctr_en : ;
252 signal stspkt_ctr_tc : ;
253 signal stspkt_ctr : (STSPKT_CTRW-1 downto 0);
258 signal status_regs_i : stat_reg_type;
259 signal sts_data : (15 downto 0);
261 signal lcl_lnk_tx_state : tx_fsm_type := RESETTING;
262 signal lcl_lnk_tx_nxt_state : tx_fsm_type;
264 alias to_ln is to_dout(16 downto 13);
265 alias to_ch is to_dout(12 downto 9);
266 signal to_tdc : (TDC_TWIDTH downto 0);
268 alias trgtag is b2tt_fifodata(47 downto 32);
269 alias atrg_sof is trg_fifo_do(trg_fifo_do'length-1);
270 alias atrg_eof is trg_fifo_do(trg_fifo_do'length-2);
271 alias daq_sof is daq_fifo_do(daq_fifo_do'length-1);
272 alias daq_eof is daq_fifo_do(daq_fifo_do'length-2);
274 signal exttb_format : (3 downto 0) := (others => '0');
278 ------------------------------------------------------------------------------------------------ 279 -- Component instantiations 280 ------------------------------------------------------------------------------------------------ 282 ------------------------------------------------------------ 283 -- Generate TDC value from trigger bits and buffer. 284 ------------------------------------------------------------ 287 -- Inputs ----------------------------- 290 reset => b2tt_runreset_tdc
(1),
291 tdc_clr => b2tt_frame2x,
--b2tt_runreset_tdc(2), 293 -- tb16 => target_tb16, 295 exttb_format => exttb_format,
296 -- Outputs ----------------------------- 298 fifo_ept => tdc_epty,
302 ------------------------------------------------------------ 303 -- Time order TDC values. 304 ------------------------------------------------------------ 305 tmodr_ins : time_order
309 reset => b2tt_runreset_tdc
(3),
310 dst_full => trg_fifo_full,
311 src_epty => tdc_epty,
318 -------------------------------------------------------------------------- 319 -- Calculate the channel word for trigger Aurora stream (convert to unified 320 -- trigger data format). 321 -------------------------------------------------------------------------- 324 NUM_CHAN => ASIC_NUM_CHAN,
325 LANEIW => to_ln'length,
326 CHANIW => to_ch'length,
327 CHANOW => trg_ch'length,
328 AXIS_VAL => AXIS_BIT_VAL
)-- Axis bit default 334 valid => trg_ch_valid,
335 axis_bit => axis_bit,
339 -------------------------------------------------------------------------- 340 -- Buffer trigger data and cross clock domain to system clock. 341 -------------------------------------------------------------------------- 342 trig_fifo_ins : trig_fifo
344 rst => b2tt_runreset,
348 wr_en => trg_fifo_we,
349 rd_en => trg_fifo_re,
351 full => trg_fifo_full,
352 almost_full => trg_fifo_afull,
353 empty => trg_fifo_epty,
354 almost_empty => trg_fifo_aepty
357 -------------------------------------------------------------------------- 359 -------------------------------------------------------------------------- 360 daq_fifo_ins : daq_fifo
363 srst => b2tt_runreset,
365 wr_en => daq_fifo_we,
366 rd_en => daq_fifo_re,
368 full => daq_fifo_full,
369 almost_full => daq_fifo_afull,
370 empty => daq_fifo_epty,
371 almost_empty => daq_fifo_aepty
374 -------------------------------------------------------- 375 -- Map signals out of the port 376 -------------------------------------------------------- 378 -------------------------------------------------------- 379 -- Combinational logic 380 -------------------------------------------------------- 381 daq_sof_d <= not (daq_sof_n or daq_src_rdy_n);
382 daq_eof_d <= not (daq_eof_n or daq_src_rdy_n);
383 daq_di_addr <= ftrgtag & daq_sof_q(1) & (not (daq_sof_n or daq_src_rdy_n));
386 fast_tdc_clk:
if USE_4NS_TDC_CLK = '1'
generate 387 to_tdc <= '0' & to_dout(TDC_TWIDTH-1 downto 0);
390 reg_tdc_clk:
if USE_4NS_TDC_CLK = '0'
generate 391 to_tdc <= to_dout(TDC_TWIDTH-1 downto 0) & '0';
395 -------------------------------------------------------------------------- 396 -- Generate external trigger 397 -------------------------------------------------------------------------- 398 exttrg_pcs :
process(tdc_clk)
400 if (tdc_clk'event and tdc_clk = '1') then 401 if b2tt_runreset_tdc(1) = '1' then 402 exttrg_ctr <= (others => '0');
405 if to_dst_we = '1' then 406 exttrg_ctr <= (others => '1');
409 if exttrg_ctr = 0 then 410 exttrg_ctr <= exttrg_ctr;
413 exttrg_ctr <= exttrg_ctr - 1;
422 -------------------------------------------------------------------------- 423 -- Deal with the b2tt interface 424 -------------------------------------------------------------------------- 425 b2tt_pcs :
process(sys_clk)
427 if (sys_clk'event and sys_clk = '1') then 428 -- get the next trigger tag value from first-word-fall-through-fifo 429 --?has not been tested, trigger processing must take 8 clocks minimum 430 if b2tt_runreset = '1' then 431 b2tt_fifonext <= '0';
433 b2tt_fifonext <= b2tt_fifordy and daq_eof_q(0);
438 -------------------------------------------------------------------------- 439 -- Write data to the trigger FIFO. Add SOF and EOF in the upper data bits. 440 -------------------------------------------------------------------------- 441 trg_wr_pcs :
process(tdc_clk)
443 if (tdc_clk'event and tdc_clk = '1') then 444 -- trigger FIFO input signals 445 -- need extend pulse to write two words 446 to_valid <= trg_ch_valid & to_valid(to_valid'length-1 downto 1);
447 -- write channel and TDC (data) 448 trg_fifo_we <= to_valid(1) or to_valid(0);
449 if to_valid(1) = '1' then 450 -- sof & eof & spare bits & data 451 trg_fifo_di <= "10" & "00000000" & axis_bit & trg_ch(trg_ch'left-1 downto 0);
453 -- sof & eof & spare bits & data 454 trg_fifo_di <= "01" & "000000" & to_tdc;
459 -------------------------------------------------------------------------- 460 -- Read data from the trigger FIFO. 461 -------------------------------------------------------------------------- 462 trg_rd_pcs :
process(sys_clk)
464 if (sys_clk'event and sys_clk = '1') then 465 trg_valid <= trg_fifo_re & trg_valid(trg_valid'length-1 downto 1);
466 if pkttp_ctr_ld = '1' then 467 trgsof_ctr <= (others => '0');
468 trgeof_ctr <= (others => '0');
470 if (trg_valid(0) and atrg_sof) = '1' then 471 trgsof_ctr <= trgsof_ctr + '1';
473 if (trg_valid(0) and atrg_eof) = '1' then 474 trgeof_ctr <= trgeof_ctr + '1';
480 -------------------------------------------------------------------------- 481 -- Write data to the DAQ FIFO. Place SOF and EOF in the upper data bits. 482 -------------------------------------------------------------------------- 483 daq_wr_pcs :
process(sys_clk)
485 if (sys_clk'event and sys_clk = '1') then 486 daq_dst_rdy_n <= daq_fifo_afull;
487 zrlentrg <= not (daq_sof_n or daq_eof_n or daq_src_rdy_n);
489 --delay two clocks so we can insert SOF marker and TRGTAG ------------ 490 daq_sof_q <= daq_sof_d & daq_sof_q(daq_sof_q'length-1 downto 1);
491 daq_eof_q <= daq_eof_d & daq_eof_q(daq_eof_q'length-1 downto 1);
492 daq_src_rdy_q <= (not daq_src_rdy_n) & daq_src_rdy_q(daq_src_rdy_q'length-1 downto 1);
493 daq_data_q <= daq_data & daq_data_q(daq_data_q'length-1 downto 1);
494 ------------------------------------------------------------------- 495 --generate write enable and extend to compensate for SOF marker and TRGTAG 496 -- daq_fifo_we <= (not daq_fifo_afull) 497 -- and (not zrlentrg) 498 -- and ((not daq_src_rdy_n) 500 -- or daq_eof_q(0));--!make sure afull provides enough delay 501 daq_fifo_we <= (not daq_fifo_afull) 508 -- select link transmit data 512 daq_fifo_di <= (not daq_sof_n) & daq_eof_q(0) & daq_data_q(0);
515 daq_fifo_di <= "10" & DAQ_SOF_VAL;
517 -- insert 16-bits of trigger tag 518 daq_fifo_di <= "00" & trgtag;
521 daq_fifo_di <= "10" & DAQ_SOF_VAL;
523 -- payload/EOF, force trigger tag & EOF when zero length 524 daq_fifo_di <= "01" & trgtag;
527 daq_fifo_di <= "10" & DAQ_SOF_VAL;
529 -- insert 16-bits of trigger tag 530 daq_fifo_di <= "00" & trgtag;
533 daq_fifo_di <= "10" & DAQ_SOF_VAL;
536 daq_fifo_di <= (others => 'X');
541 -------------------------------------------------------------------------- 542 -- Read data from the DAQ FIFO. 543 -------------------------------------------------------------------------- 544 daq_rd_pcs :
process(sys_clk)
546 if (sys_clk'event and sys_clk = '1') then 547 daq_valid <= daq_fifo_re & daq_valid(daq_valid'length-1 downto 1);
548 -- current -------------------------- 549 -- packet counter freezes 550 --daq_pause <= (atrg_eof and pkttp_ctr_tc) & daq_pause(daq_pause'length-1 downto 1); 551 ------------------------------------- 552 -- new -------------------------- 553 -- free running packet counter 554 daq_pause <= (atrg_eof and pkttp_ctr_tc) & daq_pause(daq_pause'length-1 downto 1);
555 ------------------------------------- 556 sts_pause <= daq_eof & sts_pause(sts_pause'length-1 downto 1);
557 idl_pause <= sts_eof & idl_pause(idl_pause'length-1 downto 1);
561 -------------------------------------------------------------------------- 562 -- Write status data to registers to delay. 563 -------------------------------------------------------------------------- 564 status_wr_pcs :
process(sys_clk, stspkt_ctr_en, status_upd)
566 if (sys_clk'event and sys_clk = '1') then 567 sts_sof_q <= sts_sof;
568 if stspkt_ctr_en = '0' then 569 sts_data <= STS_SOF_VAL;
571 sts_data <= status_regs_i(TO_INTEGER((stspkt_ctr)));
573 if status_upd = '1' then 574 status_regs_i <= status_regs;
579 -------------------------------------------------------------------------- 580 -- Counters for packet type logic. 581 -------------------------------------------------------------------------- 582 packet_pcs :
process(sys_clk)
584 if (sys_clk'event and sys_clk = '1') then 585 -- Trigger or DAQ packet timer 586 if pkttp_ctr_ld = '1' then 587 pkttp_ctr <= (others => '1');
590 -- current -------------------- 591 -- counter immediately terminates and stays terminated 592 -- if pkttp_ctr_tc = '0' then 593 -- pkttp_ctr <= pkttp_ctr - '1'; 595 -- if pkttp_ctr = 0 then 596 -- pkttp_ctr_tc <= '1'; 598 ---------------------------- 599 -- new --------------------- 600 -- generates a fixed time slot for trigger 601 pkttp_ctr <= pkttp_ctr - '1';
602 pkttp_ctr_tc <= pkttp_ctr(pkttp_ctr'left);
603 ---------------------------- 605 -- Counter for trigger packets for status packet decision 606 if trgpkt_ctr_ld = '1' then 607 trgpkt_ctr <= (others => '1');
608 trgpkt_ctr_tc <= '0';
610 if trgpkt_ctr_en = '1' then 611 trgpkt_ctr <= trgpkt_ctr - '1';
613 if trgpkt_ctr = 0 then 614 trgpkt_ctr_tc <= '1';
617 -- Counter for status packet length 618 if stspkt_ctr_ld = '1' then 619 stspkt_ctr <= (others=>'0');
620 stspkt_ctr_tc <= '0';
622 if (stspkt_ctr_en and (not stspkt_ctr_tc)) <= '1' then 623 stspkt_ctr <= stspkt_ctr + '1';
625 if stspkt_ctr = (NUM_SCROD_REGS-2) then 626 stspkt_ctr_tc <= '1';
632 -------------------------------------------------------------------------- 633 -- Asynchronous poriton of local link transmit state machine. Control 634 -- reading of trigger, DAQ, and status data from FIFO and the writing of 635 -- said data to the Aurora lane. Must be asynchronous because tx_dst_rdy_n 636 -- can be asserted any clock cycle. May be able to use warn_cc signal to 637 -- pause transmit so no link errors occur. 638 --?Unlikely this will meet timing, but try to keep trigger data latency low. 639 -------------------------------------------------------------------------- 640 ll_tx_fsm_a :
process(lcl_lnk_tx_state, tx_dst_rdy_n, pkttp_ctr_tc, trg_fifo_epty,
641 daq_fifo_epty, atrg_sof, atrg_eof, daq_sof, daq_eof,
642 trgpkt_ctr_tc, trg_fifo_do, daq_fifo_do, daq_pause(
0),
643 stspkt_ctr_tc, sts_data, sts_pause, idl_pause, sts_eof,
644 status_upd, trgsof_ctr, sts_sof_q)
646 -- Default values (use less lines) 648 trgpkt_ctr_ld <= '0';
649 trgpkt_ctr_en <= '0';
650 stspkt_ctr_ld <= '1';
651 stspkt_ctr_en <= '0';
659 --tx_src_rdy_n <= '1'; 660 tx_data <= (others => '1');
661 stat_tx_in_progress <= '0';
663 case lcl_lnk_tx_state is 666 trgpkt_ctr_ld <= '1';
667 trgpkt_ctr_en <= '0';
668 stspkt_ctr_ld <= '1';
676 --tx_src_rdy_n <= '1'; 677 tx_data <= (others => '1');
678 lcl_lnk_tx_nxt_state <= IDLE;
679 -- stat_tx_in_progress <= '0'; 681 -- wait until FIFO has data and Aurora ready 683 -- trig ==> daq ==> status 684 if tx_dst_rdy_n = '0' then 685 if pkttp_ctr_tc = '0' then 686 if trg_fifo_epty = '0' then 687 lcl_lnk_tx_nxt_state <= SEND_TRIG_SOF;
689 lcl_lnk_tx_nxt_state <= IDLE;
692 if daq_fifo_epty = '0' then 693 lcl_lnk_tx_nxt_state <= SEND_DAQ_SOF;
695 if status_upd = '1' then 696 lcl_lnk_tx_nxt_state <= SEND_STATUS_SOF;
698 lcl_lnk_tx_nxt_state <= IDLE;
703 lcl_lnk_tx_nxt_state <= IDLE;
705 when SEND_TRIG_SOF => 706 -- make sure trigger SOF is read 707 trg_fifo_re <= (not tx_dst_rdy_n) and (not trg_fifo_epty) and (not atrg_sof);
708 if ((not tx_dst_rdy_n) and atrg_sof) = '1' then 709 -- make sure SOF was read 711 --tx_src_rdy_n <= '0'; 712 lcl_lnk_tx_nxt_state <= SEND_TRIG_PAYLOADS;
713 tx_data <= TRG_SOF_VAL;
-- insert trigger SOF value 717 --tx_src_rdy_n <= '1'; 718 lcl_lnk_tx_nxt_state <=SEND_TRIG_SOF;
719 tx_data <= trg_fifo_do(15 downto 0);
-- FIFO data 721 --tx_data <= trg_fifo_do(15 downto 0); 722 when SEND_TRIG_PAYLOADS => 723 -- make sure the trigger payload is read until EOF 724 trg_fifo_re <= (not tx_dst_rdy_n) and (not trg_fifo_epty) and (not (atrg_eof and pkttp_ctr_tc));
725 --tx_src_rdy_n <= tx_dst_rdy_n or trg_fifo_epty; 726 if ((not tx_dst_rdy_n) and (atrg_eof and pkttp_ctr_tc)) = '1' then 727 -- make sure EOF was read 728 --tx_eof_n <= '0';--g 730 lcl_lnk_tx_nxt_state <= SEND_TRIG_EOF;
732 -- keep reading otherwise 733 --tx_eof_n <= '1';--g 735 lcl_lnk_tx_nxt_state <= SEND_TRIG_PAYLOADS;
737 tx_data <= trg_fifo_do(15 downto 0);
738 when SEND_TRIG_EOF => 739 -- write EOF and counters for debug 740 --tx_eof_n <= '0';--n 741 tx_eof_n <= not (daq_pause(daq_pause'length-1) and (not daq_pause(daq_pause'length-2)));
--n 742 -- current -------------------------- 743 -- packet counter freezes 744 --pkttp_ctr_ld <= '1';-- use for pause 745 ------------------------------------- 746 -- new ------------------------------- 747 -- fixed trigger window, free running counter 748 -- do nothing, default sets pkttp_ctr_ld <= '0' 749 -------------------------------------- 750 -- where do we go next? - send status if sent enough trigger packets and DAQ ZLT 751 if daq_pause(0) = '1' then 752 if daq_fifo_epty = '0' then 753 lcl_lnk_tx_nxt_state <= SEND_DAQ_SOF;
755 lcl_lnk_tx_nxt_state <= IDLE;
758 lcl_lnk_tx_nxt_state <= SEND_TRIG_EOF;
760 tx_data <= trgsof_ctr & trgeof_ctr;
762 -- make sure DAQ SOF is read 764 daq_fifo_re <= (not tx_dst_rdy_n) and (not daq_fifo_epty) and (not daq_sof);
765 if ((not tx_dst_rdy_n) and daq_sof) = '1' then 767 --tx_src_rdy_n <= '0'; 768 trgpkt_ctr_en <= '1';
769 lcl_lnk_tx_nxt_state <= SEND_DAQ_PAYLOADS;
772 --tx_src_rdy_n <= '1'; 773 trgpkt_ctr_en <= '0';
774 lcl_lnk_tx_nxt_state <= SEND_DAQ_SOF;
776 tx_data <= daq_fifo_do(15 downto 0);
777 when SEND_DAQ_PAYLOADS => 778 -- make sure the DAQ payload is read until EOF 780 daq_fifo_re <= (not tx_dst_rdy_n) and (not daq_fifo_epty) and (not daq_eof);
781 --tx_src_rdy_n <= tx_dst_rdy_n or daq_fifo_epty; 782 --if ((not tx_dst_rdy_n) and daq_eof) = '1' then--g 783 tx_eof_n <= not (daq_eof and (not sts_pause(sts_pause'length-1)));
784 if ((not tx_dst_rdy_n) and daq_eof and sts_pause(0)) = '1' then --n 785 --tx_eof_n <= '0';--g 786 if trgpkt_ctr_tc = '1' then --g 787 lcl_lnk_tx_nxt_state <= SEND_STATUS_SOF;
789 lcl_lnk_tx_nxt_state <= IDLE;
792 --tx_eof_n <= '1';--g 793 lcl_lnk_tx_nxt_state <= SEND_DAQ_PAYLOADS;
795 tx_data <= daq_fifo_do(15 downto 0);
796 when SEND_STATUS_SOF => 797 -- send start of frame (SOF) 799 trgpkt_ctr_ld <= '1';
801 if ((not tx_dst_rdy_n) and sts_sof_q) = '1' then 803 lcl_lnk_tx_nxt_state <= SEND_STATUS_PAYLOADS;
806 lcl_lnk_tx_nxt_state <= SEND_STATUS_SOF;
809 when SEND_STATUS_PAYLOADS => 810 stat_tx_in_progress <= '1';
812 trgpkt_ctr_ld <= '1';
813 stspkt_ctr_ld <= '0';
814 --tx_eof_n <= not (stspkt_ctr_tc and (not idl_pause(idl_pause'length-1)));-- sts_eof;--gish 815 tx_eof_n <= not (stspkt_ctr_tc and (not OR_REDUCE(idl_pause)));
--n 816 stspkt_ctr_en <= (not tx_dst_rdy_n) and (not stspkt_ctr_tc);
817 sts_eof <= (not tx_dst_rdy_n) and stspkt_ctr_tc;
818 if idl_pause(0) = '1' then --n 819 lcl_lnk_tx_nxt_state <= IDLE;
821 lcl_lnk_tx_nxt_state <= SEND_STATUS_PAYLOADS;
825 lcl_lnk_tx_nxt_state <= IDLE;
829 -------------------------------------------------------------------------- 830 -- Synchronous portion of local link transmit state machine. 831 -------------------------------------------------------------------------- 832 ll_tx_fsm_s :
process(sys_clk)
834 if (sys_clk'event and sys_clk = '1') then 835 if b2tt_runreset = '1' then 836 lcl_lnk_tx_state <= RESETTING;
838 lcl_lnk_tx_state <= lcl_lnk_tx_nxt_state;
843 ------------------------------------------------------------------ 844 -- Generate the local link signals. Make something sensible of 845 -- the state machine outputs. 846 ------------------------------------------------------------------ 847 ll_tx_pcs :
process(sys_clk)
849 if (sys_clk'event and sys_clk = '1') then 850 --use atrg_sof to inject trigger SOF word, delay read enable signals 851 -- so FIFO out if valid 853 --tx_src_rdy_n <= not (trg_fifo_re or daq_fifo_re); 854 --tx_src_rdy_n <= not (atrg_sof or trg_fifo_re or daq_fifo_re); 855 tx_src_rdy_n <= not (atrg_sof 859 or (sts_sof and (not sts_sof_q)) 864 ------------------------------------------------------------------ 865 -- Recieve data from the Aurora lane and write to the run control 867 ------------------------------------------------------------------ 868 ll_rx_pcs :
process(sys_clk)
870 if (sys_clk'event and sys_clk = '1') then 871 --?just pass it through for now 872 -- rx_dst_rdy_n <= rcl_dst_rdy_n; 873 -- rcl_sof_n <= rx_sof_n; 874 -- rcl_eof_n <= rx_eof_n; 875 rcl_src_rdy_n <= rx_src_rdy_n;
881 --------------------------------------------------------------------------------------------------------