Belle II KLM Scint Firmware  1
conc_intfc.vhd
1 --*********************************************************************************
2 -- Indiana University CEEM
3 -- Project: Belle-II
4 -- Author: Brandon Kunkler
5 -- Date: 06/09/2014
6 --*********************************************************************************
7 -- ### conc_intfc.vhd
8 -- ##### Description:
9 -- Reads trigger and DAQ packets from the scintillator electronics. The trigger
10 -- packets are comprised of of many smaller raw samples. Trigger raw samples are
11 -- channel and time. DAQ packets are an entire triggers worth of data. Data bandwith
12 -- is increased by not using the overhead of marking each raw sample on the link.
13 -- A pause should be inserted after the sof_n signal is asserted and ~4 pauses should
14 -- be inserted after eof_n is asserted.
15 --
16 -- ##### Deficiencies/Issues
17 -- 1. Will drop a word if a clock correction sequence occurs during the middle of
18 -- a packet. Need to re-transmit if tx_dst_rdy_n is asserted while tx_src_rdy_n
19 -- is asserted. Could tranistion to a wait state that keeps all local link signals
20 -- the same until tx_dst_rdy_n is de-asserted. Or, could use the do_cc and warn_cc
21 -- signals to prevent sending data when tx_dst_rdy_n is going to be asserted.
22 -- 2. Does nothing with run control registers (may not matter).
23 -- 3. Does nothing with status registers.
24 -- 4. Need to add assertions to make sure no FIFO read or write errors occur.
25 -- 5. WARNING:HDLCompiler:746 - "/home/cketter/klm/firmware/klm_scrod/conc_intfc/source/conc_intfc.vhd"
26 -- Line 460: Range is empty (null range) --- trg_valid <= trg_fifo_re & trg_valid(trg_valid'length-1 downto 1);
27 -- I'm surprised this is not an error.
28 -- Need to evaluate importance of this signal and underlying logic. Seems to affect
29 -- trig Start-Of-Frame and End-Of-Frame sent to DC. (CK)
30 
31 --*********************************************************************************
32 library ieee;
33  use ieee.std_logic_1164.all;
34  use ieee.std_logic_unsigned.all;
35  use ieee.numeric_std.all;
36  use ieee.std_logic_misc.all;
37 library work;
38  use work.time_order_pkg.all;
39  use work.tdc_pkg.all;
40  use work.conc_intfc_pkg.all;
41 
42 entity conc_intfc is
43  generic(
44  USE_4NS_TDC_CLK : std_logic := '0'
45  );
46  port(
47  -- inputs ---------------------------------------------
48  sys_clk : in std_logic;
49  tdc_clk : in std_logic;
50  ce : in std_logic_vector(1 to 5);
51  --B2TT interface
52  b2tt_runreset : in std_logic;
53  b2tt_runreset_tdc : in std_logic_vector(1 to 3);
54  b2tt_gtpreset : in std_logic;
55  b2tt_frame2x : in std_logic;
56  b2tt_fifordy : in std_logic;
57  b2tt_fifodata : in std_logic_vector (95 downto 0);
58  b2tt_fifonext : out std_logic;
59  --TARGET ASIC trigger interface (trigger bits)
60  target_tb : in tb_vec_type;
61  -- target_tb16 : in std_logic_vector(1 to TDC_NASICS);
62  -- status sent to concentrator
63  status_upd : in std_logic;
64  stat_tx_in_progress : out std_logic;
65  status_regs : in stat_reg_type;
66  -- Aurora local input local link (from Concentrator)
67  -- rx_dst_rdy_n : out std_logic;
68  -- rx_sof_n : in std_logic;
69  -- rx_eof_n : in std_logic;
70  rx_src_rdy_n : in std_logic;
71  rx_data : in std_logic_vector(15 downto 0);
72  -- DAQ data local link input (TARGET DAQ data when triggered)
73  daq_dst_rdy_n : out std_logic;
74  daq_sof_n : in std_logic;--start of trigger
75  daq_eof_n : in std_logic;--end of trigger
76  daq_src_rdy_n : in std_logic;
77  daq_data : in std_logic_vector(15 downto 0);
78  -- outputs --------------------------------------------
79  exttrg : out std_logic := '0';
80  exttb : out tb_vec_type;
81  -- Aurora local ouptput local link (to Concentrator)
82  tx_dst_rdy_n : in std_logic;
83  tx_sof_n : out std_logic;
84  tx_eof_n : out std_logic;
85  tx_src_rdy_n : out std_logic;
86  tx_data : out std_logic_vector(15 downto 0);
87  -- Run control local link output
88  -- rcl_dst_rdy_n : in std_logic;
89  -- rcl_sof_n : out std_logic := '1';
90  -- rcl_eof_n : out std_logic := '1';
91  rcl_src_rdy_n : out std_logic := '1';
92  rcl_data : out std_logic_vector(15 downto 0));
93 end conc_intfc;
94 
95 architecture behave of conc_intfc is
96 
97  component tdc is
98  port(
99  -- Inputs -----------------------------
100  tdc_clk : in std_logic;
101  ce : in std_logic_vector(1 to 4);
102  reset : in std_logic;
103  tdc_clr : in std_logic;
104  tb : in tb_vec_type;
105  -- tb16 : in std_logic_vector(1 to TDC_NASICS);
106  fifo_re : in std_logic_vector(1 to TDC_NASICS);
107  exttb_format : in std_logic_vector(3 downto 0);
108  -- Outputs -----------------------------
109  exttb : out tb_vec_type;
110  fifo_ept : out std_logic_vector(1 to TDC_NASICS);
111  tdc_dout : out tdc_dout_type);
112  end component;
113 
114  component time_order is
115  port(
116  clk : in std_logic;
117  ce : in std_logic;
118  reset : in std_logic;
119  dst_full : in std_logic;
120  src_epty : in std_logic_vector(1 to TO_NUM_LANES);
121  din : in tdc_dout_type;
122  src_re : out std_logic_vector(1 to TO_NUM_LANES);
123  dst_we : out std_logic;
124  dout : out std_logic_vector(TO_WIDTH-1 downto 0));
125  end component;
126 
127  component trig_chan_calc is
128  generic(
129  NUM_CHAN : integer; -- ASIC channels
130  LANEIW : integer; -- Lane in width
131  CHANIW : integer; -- Channel in width
132  CHANOW : integer; -- Channel out width
133  AXIS_VAL : std_logic);-- Axis bit default
134  port(
135  -- inputs ---------------------------------------------
136  clk : in std_logic;
137  we : in std_logic;
138  lane : in std_logic_vector(LANEIW-1 downto 0);
139  chan : in std_logic_vector(CHANIW-1 downto 0);
140  valid : out std_logic;
141  axis_bit : out std_logic;
142  trig_chan : out std_logic_vector(CHANOW-1 downto 0));
143  end component;
144 
145  component trig_fifo
146  port (
147  rst : in std_logic;
148  wr_clk : in std_logic;
149  rd_clk : in std_logic;
150  din : in std_logic_vector(17 downto 0);
151  wr_en : in std_logic;
152  rd_en : in std_logic;
153  dout : out std_logic_vector(17 downto 0);
154  full : out std_logic;
155  almost_full : out std_logic;
156  empty : out std_logic;
157  almost_empty : out std_logic);
158  end component;
159 
160  component daq_fifo
161  port (
162  clk : in std_logic;
163  srst : in std_logic;
164  din : in std_logic_vector(17 downto 0);
165  wr_en : in std_logic;
166  rd_en : in std_logic;
167  dout : out std_logic_vector(17 downto 0);
168  full : out std_logic;
169  almost_full : out std_logic;
170  empty : out std_logic;
171  almost_empty : out std_logic);
172  end component;
173 
174  type tx_fsm_type is (
175  RESETTING,
176  IDLE,
177  SEND_TRIG_SOF,
178  SEND_TRIG_PAYLOADS,
179  SEND_DAQ_SOF,
180  SEND_DAQ_PAYLOADS,
181  SEND_TRIG_EOF,
182  SEND_STATUS_SOF,
183  SEND_STATUS_PAYLOADS
184  );
185  type word_shift_type is array (natural range <> ) of std_logic_vector(15 downto 0);
186 
187  signal exttrg_ctr : std_logic_vector(3 downto 0) := (others => '0');
188 
189  signal tdc_rden : std_logic_vector(1 to TDC_NASICS);
190  signal tdc_epty : std_logic_vector(1 to TDC_NASICS);
191  signal tdc_dout : tdc_dout_type;
192 
193  signal to_dst_we : std_logic;
194  signal to_dout : std_logic_vector(TO_WIDTH-1 downto 0);
195  signal to_valid : std_logic_vector(1 downto 0);
196 
197  signal trg_fifo_we : std_logic := '0';
198  signal trg_fifo_di : std_logic_vector(17 downto 0);
199  signal trg_fifo_re : std_logic;
200  signal trg_fifo_do : std_logic_vector(17 downto 0);
201  signal trg_fifo_afull : std_logic;
202  signal trg_fifo_epty : std_logic;
203  signal trg_fifo_aepty : std_logic;
204  signal trg_fifo_full : std_logic;
205  -- signal trg_fifo_rderr : std_logic;
206  -- signal trg_fifo_wrerr : std_logic;
207 
208  signal daq_fifo_we : std_logic := '0';
209  signal daq_fifo_di : std_logic_vector(17 downto 0);
210  signal daq_fifo_re : std_logic;
211  signal daq_fifo_do : std_logic_vector(17 downto 0);
212  signal daq_fifo_afull : std_logic;
213  signal daq_fifo_epty : std_logic;
214  signal daq_fifo_aepty : std_logic;
215  signal daq_fifo_full : std_logic;
216  -- signal daq_fifo_rderr : std_logic;
217  -- signal daq_fifo_wrerr : std_logic;
218 
219  signal axis_bit : std_logic;
220  signal trg_ch : std_logic_vector(7 downto 0);
221  signal trg_ch_valid : std_logic;
222  signal strg_eof : std_logic;
223  signal trg_valid : std_logic_vector(0 downto 0);
224  signal trgsof_ctr : std_logic_vector(7 downto 0);
225  signal trgeof_ctr : std_logic_vector(7 downto 0);
226 
227  signal zrlentrg : std_logic;
228  signal ftrgtag : std_logic;
229  signal daq_sof_d : std_logic;
230  signal daq_eof_d : std_logic;
231  signal daq_sof_q : std_logic_vector(1 downto 0);
232  signal daq_eof_q : std_logic_vector(1 downto 0);
233  signal daq_src_rdy_q : std_logic_vector(1 downto 0);
234  signal daq_data_q : word_shift_type(1 downto 0);
235  signal daq_valid : std_logic_vector(2 downto 0);
236  signal daq_di_addr : std_logic_vector(2 downto 0);
237  signal daq_pause : std_logic_vector(3 downto 0);
238  signal sts_pause : std_logic_vector(1 downto 0);
239  signal idl_pause : std_logic_vector(1 downto 0);
240 
241 
242  -- pakcet type counter (time spent writing trigger data) - just change the width to adjust
243  signal pkttp_ctr_ld : std_logic;
244  signal pkttp_ctr_tc : std_logic;
245  signal pkttp_ctr : std_logic_vector(PKTTP_CTRW-1 downto 0);
246  signal trgpkt_ctr_ld : std_logic;
247  signal trgpkt_ctr_en : std_logic;
248  signal trgpkt_ctr_tc : std_logic;
249  signal trgpkt_ctr : std_logic_vector(TGPKT_CTRW-1 downto 0);
250  signal stspkt_ctr_ld : std_logic;
251  signal stspkt_ctr_en : std_logic;
252  signal stspkt_ctr_tc : std_logic;
253  signal stspkt_ctr : std_logic_vector(STSPKT_CTRW-1 downto 0);
254 
255  signal sts_sof : std_logic;
256  signal sts_eof : std_logic;
257  signal sts_sof_q : std_logic;
258  signal status_regs_i : stat_reg_type;
259  signal sts_data : std_logic_vector(15 downto 0);
260 
261  signal lcl_lnk_tx_state : tx_fsm_type := RESETTING;
262  signal lcl_lnk_tx_nxt_state : tx_fsm_type;
263 
264  alias to_ln is to_dout(16 downto 13);
265  alias to_ch is to_dout(12 downto 9);
266  signal to_tdc : std_logic_vector(TDC_TWIDTH downto 0);
267 
268  alias trgtag is b2tt_fifodata(47 downto 32);
269  alias atrg_sof is trg_fifo_do(trg_fifo_do'length-1);
270  alias atrg_eof is trg_fifo_do(trg_fifo_do'length-2);
271  alias daq_sof is daq_fifo_do(daq_fifo_do'length-1);
272  alias daq_eof is daq_fifo_do(daq_fifo_do'length-2);
273 
274  signal exttb_format : std_logic_vector(3 downto 0) := (others => '0');
275 
276 begin
277 
278 ------------------------------------------------------------------------------------------------
279 -- Component instantiations
280 ------------------------------------------------------------------------------------------------
281 
282  ------------------------------------------------------------
283  -- Generate TDC value from trigger bits and buffer.
284  ------------------------------------------------------------
285  tdc_ins : tdc
286  port map(
287  -- Inputs -----------------------------
288  tdc_clk => tdc_clk,
289  ce => ce(1 to 4),
290  reset => b2tt_runreset_tdc(1),
291  tdc_clr => b2tt_frame2x,--b2tt_runreset_tdc(2),
292  tb => target_tb,
293  -- tb16 => target_tb16,
294  fifo_re => tdc_rden,
295  exttb_format => exttb_format,
296  -- Outputs -----------------------------
297  exttb => exttb,
298  fifo_ept => tdc_epty,
299  tdc_dout => tdc_dout
300  );
301 
302  ------------------------------------------------------------
303  -- Time order TDC values.
304  ------------------------------------------------------------
305  tmodr_ins : time_order
306  port map(
307  clk => tdc_clk,
308  ce => ce(5),
309  reset => b2tt_runreset_tdc(3),
310  dst_full => trg_fifo_full,
311  src_epty => tdc_epty,
312  din => tdc_dout,
313  src_re => tdc_rden,
314  dst_we => to_dst_we,
315  dout => to_dout
316  );
317 
318  --------------------------------------------------------------------------
319  -- Calculate the channel word for trigger Aurora stream (convert to unified
320  -- trigger data format).
321  --------------------------------------------------------------------------
322  trg_chan_ins : trig_chan_calc
323  generic map(
324  NUM_CHAN => ASIC_NUM_CHAN,
325  LANEIW => to_ln'length,
326  CHANIW => to_ch'length,
327  CHANOW => trg_ch'length,
328  AXIS_VAL => AXIS_BIT_VAL)-- Axis bit default
329  port map(
330  clk => tdc_clk,
331  we => to_dst_we,
332  lane => to_ln,
333  chan => to_ch,
334  valid => trg_ch_valid,
335  axis_bit => axis_bit,
336  trig_chan => trg_ch
337  );
338 
339  --------------------------------------------------------------------------
340  -- Buffer trigger data and cross clock domain to system clock.
341  --------------------------------------------------------------------------
342  trig_fifo_ins : trig_fifo
343  port map(
344  rst => b2tt_runreset,
345  wr_clk => tdc_clk,
346  rd_clk => sys_clk,
347  din => trg_fifo_di,
348  wr_en => trg_fifo_we,
349  rd_en => trg_fifo_re,
350  dout => trg_fifo_do,
351  full => trg_fifo_full,
352  almost_full => trg_fifo_afull,
353  empty => trg_fifo_epty,
354  almost_empty => trg_fifo_aepty
355  );
356 
357  --------------------------------------------------------------------------
358  -- Buffer DAQ data.
359  --------------------------------------------------------------------------
360  daq_fifo_ins : daq_fifo
361  port map(
362  clk => sys_clk,
363  srst => b2tt_runreset,
364  din => daq_fifo_di,
365  wr_en => daq_fifo_we,
366  rd_en => daq_fifo_re,
367  dout => daq_fifo_do,
368  full => daq_fifo_full,
369  almost_full => daq_fifo_afull,
370  empty => daq_fifo_epty,
371  almost_empty => daq_fifo_aepty
372  );
373 
374  --------------------------------------------------------
375  -- Map signals out of the port
376  --------------------------------------------------------
377 
378  --------------------------------------------------------
379  -- Combinational logic
380  --------------------------------------------------------
381  daq_sof_d <= not (daq_sof_n or daq_src_rdy_n);
382  daq_eof_d <= not (daq_eof_n or daq_src_rdy_n);
383  daq_di_addr <= ftrgtag & daq_sof_q(1) & (not (daq_sof_n or daq_src_rdy_n));
384 
385 
386  fast_tdc_clk: if USE_4NS_TDC_CLK = '1' generate
387  to_tdc <= '0' & to_dout(TDC_TWIDTH-1 downto 0);
388  end generate;
389 
390  reg_tdc_clk: if USE_4NS_TDC_CLK = '0' generate
391  to_tdc <= to_dout(TDC_TWIDTH-1 downto 0) & '0';
392  end generate;
393 
394 
395  --------------------------------------------------------------------------
396  -- Generate external trigger
397  --------------------------------------------------------------------------
398  exttrg_pcs : process(tdc_clk)
399  begin
400  if (tdc_clk'event and tdc_clk = '1') then
401  if b2tt_runreset_tdc(1) = '1' then
402  exttrg_ctr <= (others => '0');
403  exttrg <= '0';
404  else
405  if to_dst_we = '1' then
406  exttrg_ctr <= (others => '1');
407  exttrg <= '1';
408  else
409  if exttrg_ctr = 0 then
410  exttrg_ctr <= exttrg_ctr;
411  exttrg <= '0';
412  else
413  exttrg_ctr <= exttrg_ctr - 1;
414  exttrg <= '1';
415  end if;
416  end if;
417  end if;
418  end if;
419  end process;
420 
421 
422  --------------------------------------------------------------------------
423  -- Deal with the b2tt interface
424  --------------------------------------------------------------------------
425  b2tt_pcs : process(sys_clk)
426  begin
427  if (sys_clk'event and sys_clk = '1') then
428  -- get the next trigger tag value from first-word-fall-through-fifo
429  --?has not been tested, trigger processing must take 8 clocks minimum
430  if b2tt_runreset = '1' then
431  b2tt_fifonext <= '0';
432  else
433  b2tt_fifonext <= b2tt_fifordy and daq_eof_q(0);
434  end if;
435  end if;
436  end process;
437 
438  --------------------------------------------------------------------------
439  -- Write data to the trigger FIFO. Add SOF and EOF in the upper data bits.
440  --------------------------------------------------------------------------
441  trg_wr_pcs : process(tdc_clk)
442  begin
443  if (tdc_clk'event and tdc_clk = '1') then
444  -- trigger FIFO input signals
445  -- need extend pulse to write two words
446  to_valid <= trg_ch_valid & to_valid(to_valid'length-1 downto 1);
447  -- write channel and TDC (data)
448  trg_fifo_we <= to_valid(1) or to_valid(0);
449  if to_valid(1) = '1' then
450  -- sof & eof & spare bits & data
451  trg_fifo_di <= "10" & "00000000" & axis_bit & trg_ch(trg_ch'left-1 downto 0);
452  else
453  -- sof & eof & spare bits & data
454  trg_fifo_di <= "01" & "000000" & to_tdc;
455  end if;
456  end if;
457  end process;
458 
459  --------------------------------------------------------------------------
460  -- Read data from the trigger FIFO.
461  --------------------------------------------------------------------------
462  trg_rd_pcs : process(sys_clk)
463  begin
464  if (sys_clk'event and sys_clk = '1') then
465  trg_valid <= trg_fifo_re & trg_valid(trg_valid'length-1 downto 1);
466  if pkttp_ctr_ld = '1' then
467  trgsof_ctr <= (others => '0');
468  trgeof_ctr <= (others => '0');
469  else
470  if (trg_valid(0) and atrg_sof) = '1' then
471  trgsof_ctr <= trgsof_ctr + '1';
472  end if;
473  if (trg_valid(0) and atrg_eof) = '1' then
474  trgeof_ctr <= trgeof_ctr + '1';
475  end if;
476  end if;
477  end if;
478  end process;
479 
480  --------------------------------------------------------------------------
481  -- Write data to the DAQ FIFO. Place SOF and EOF in the upper data bits.
482  --------------------------------------------------------------------------
483  daq_wr_pcs : process(sys_clk)
484  begin
485  if (sys_clk'event and sys_clk = '1') then
486  daq_dst_rdy_n <= daq_fifo_afull;
487  zrlentrg <= not (daq_sof_n or daq_eof_n or daq_src_rdy_n);
488  ftrgtag <= zrlentrg;
489  --delay two clocks so we can insert SOF marker and TRGTAG ------------
490  daq_sof_q <= daq_sof_d & daq_sof_q(daq_sof_q'length-1 downto 1);
491  daq_eof_q <= daq_eof_d & daq_eof_q(daq_eof_q'length-1 downto 1);
492  daq_src_rdy_q <= (not daq_src_rdy_n) & daq_src_rdy_q(daq_src_rdy_q'length-1 downto 1);
493  daq_data_q <= daq_data & daq_data_q(daq_data_q'length-1 downto 1);
494  -------------------------------------------------------------------
495  --generate write enable and extend to compensate for SOF marker and TRGTAG
496  -- daq_fifo_we <= (not daq_fifo_afull)
497  -- and (not zrlentrg)
498  -- and ((not daq_src_rdy_n)
499  -- or daq_eof_q(1)
500  -- or daq_eof_q(0));--!make sure afull provides enough delay
501  daq_fifo_we <= (not daq_fifo_afull)
502  and (not zrlentrg)
503  and (daq_sof_d
504  or daq_sof_q(1)
505  or daq_src_rdy_q(0)
506  or daq_eof_q(1)
507  or daq_eof_q(0));
508  -- select link transmit data
509  case daq_di_addr is
510  when "000" =>
511  -- payload/EOF
512  daq_fifo_di <= (not daq_sof_n) & daq_eof_q(0) & daq_data_q(0);
513  when "001" =>
514  -- insert SOF marker
515  daq_fifo_di <= "10" & DAQ_SOF_VAL;
516  when "010" =>
517  -- insert 16-bits of trigger tag
518  daq_fifo_di <= "00" & trgtag;
519  when "011" =>
520  -- should not happen
521  daq_fifo_di <= "10" & DAQ_SOF_VAL;
522  when "100" =>
523  -- payload/EOF, force trigger tag & EOF when zero length
524  daq_fifo_di <= "01" & trgtag;
525  when "101" =>
526  -- insert SOF marker
527  daq_fifo_di <= "10" & DAQ_SOF_VAL;
528  when "110" =>
529  -- insert 16-bits of trigger tag
530  daq_fifo_di <= "00" & trgtag;
531  when "111" =>
532  -- should not happen
533  daq_fifo_di <= "10" & DAQ_SOF_VAL;
534  when others =>
535  -- will not happen
536  daq_fifo_di <= (others => 'X');
537  end case;
538  end if;
539  end process;
540 
541  --------------------------------------------------------------------------
542  -- Read data from the DAQ FIFO.
543  --------------------------------------------------------------------------
544  daq_rd_pcs : process(sys_clk)
545  begin
546  if (sys_clk'event and sys_clk = '1') then
547  daq_valid <= daq_fifo_re & daq_valid(daq_valid'length-1 downto 1);
548  -- current --------------------------
549  -- packet counter freezes
550  --daq_pause <= (atrg_eof and pkttp_ctr_tc) & daq_pause(daq_pause'length-1 downto 1);
551  -------------------------------------
552  -- new --------------------------
553  -- free running packet counter
554  daq_pause <= (atrg_eof and pkttp_ctr_tc) & daq_pause(daq_pause'length-1 downto 1);
555  -------------------------------------
556  sts_pause <= daq_eof & sts_pause(sts_pause'length-1 downto 1);
557  idl_pause <= sts_eof & idl_pause(idl_pause'length-1 downto 1);
558  end if;
559  end process;
560 
561  --------------------------------------------------------------------------
562  -- Write status data to registers to delay.
563  --------------------------------------------------------------------------
564  status_wr_pcs : process(sys_clk, stspkt_ctr_en, status_upd)
565  begin
566  if (sys_clk'event and sys_clk = '1') then
567  sts_sof_q <= sts_sof;
568  if stspkt_ctr_en = '0' then
569  sts_data <= STS_SOF_VAL;
570  else
571  sts_data <= status_regs_i(TO_INTEGER(UNSIGNED(stspkt_ctr)));
572  end if;
573  if status_upd = '1' then
574  status_regs_i <= status_regs;
575  end if;
576  end if;
577  end process;
578 
579  --------------------------------------------------------------------------
580  -- Counters for packet type logic.
581  --------------------------------------------------------------------------
582  packet_pcs : process(sys_clk)
583  begin
584  if (sys_clk'event and sys_clk = '1') then
585  -- Trigger or DAQ packet timer
586  if pkttp_ctr_ld = '1' then
587  pkttp_ctr <= (others => '1');
588  pkttp_ctr_tc <= '0';
589  else
590  -- current --------------------
591  -- counter immediately terminates and stays terminated
592  -- if pkttp_ctr_tc = '0' then
593  -- pkttp_ctr <= pkttp_ctr - '1';
594  -- end if;
595  -- if pkttp_ctr = 0 then
596  -- pkttp_ctr_tc <= '1';
597  -- end if;
598  ----------------------------
599  -- new ---------------------
600  -- generates a fixed time slot for trigger
601  pkttp_ctr <= pkttp_ctr - '1';
602  pkttp_ctr_tc <= pkttp_ctr(pkttp_ctr'left);
603  ----------------------------
604  end if;
605  -- Counter for trigger packets for status packet decision
606  if trgpkt_ctr_ld = '1' then
607  trgpkt_ctr <= (others => '1');
608  trgpkt_ctr_tc <= '0';
609  else
610  if trgpkt_ctr_en = '1' then
611  trgpkt_ctr <= trgpkt_ctr - '1';
612  end if;
613  if trgpkt_ctr = 0 then
614  trgpkt_ctr_tc <= '1';
615  end if;
616  end if;
617  -- Counter for status packet length
618  if stspkt_ctr_ld = '1' then
619  stspkt_ctr <= (others=>'0');
620  stspkt_ctr_tc <= '0';
621  else
622  if (stspkt_ctr_en and (not stspkt_ctr_tc)) <= '1' then
623  stspkt_ctr <= stspkt_ctr + '1';
624  end if;
625  if stspkt_ctr = (NUM_SCROD_REGS-2) then
626  stspkt_ctr_tc <= '1';
627  end if;
628  end if;
629  end if;
630  end process;
631 
632  --------------------------------------------------------------------------
633  -- Asynchronous poriton of local link transmit state machine. Control
634  -- reading of trigger, DAQ, and status data from FIFO and the writing of
635  -- said data to the Aurora lane. Must be asynchronous because tx_dst_rdy_n
636  -- can be asserted any clock cycle. May be able to use warn_cc signal to
637  -- pause transmit so no link errors occur.
638  --?Unlikely this will meet timing, but try to keep trigger data latency low.
639  --------------------------------------------------------------------------
640  ll_tx_fsm_a : process(lcl_lnk_tx_state, tx_dst_rdy_n, pkttp_ctr_tc, trg_fifo_epty,
641  daq_fifo_epty, atrg_sof, atrg_eof, daq_sof, daq_eof,
642  trgpkt_ctr_tc, trg_fifo_do, daq_fifo_do, daq_pause(0),
643  stspkt_ctr_tc, sts_data, sts_pause, idl_pause, sts_eof,
644  status_upd, trgsof_ctr, sts_sof_q)
645  begin
646  -- Default values (use less lines)
647  pkttp_ctr_ld <= '0';
648  trgpkt_ctr_ld <= '0';
649  trgpkt_ctr_en <= '0';
650  stspkt_ctr_ld <= '1';
651  stspkt_ctr_en <= '0';
652  strg_eof <= '0';
653  sts_sof <= '0';
654  sts_eof <= '0';
655  trg_fifo_re <= '0';
656  daq_fifo_re <= '0';
657  tx_sof_n <= '1';
658  tx_eof_n <= '1';
659  --tx_src_rdy_n <= '1';
660  tx_data <= (others => '1');
661  stat_tx_in_progress <= '0';
662 
663  case lcl_lnk_tx_state is
664  when RESETTING =>
665  pkttp_ctr_ld <= '1';
666  trgpkt_ctr_ld <= '1';
667  trgpkt_ctr_en <= '0';
668  stspkt_ctr_ld <= '1';
669  strg_eof <= '0';
670  sts_sof <= '0';
671  sts_eof <= '0';
672  trg_fifo_re <= '0';
673  daq_fifo_re <= '0';
674  tx_sof_n <= '1';
675  tx_eof_n <= '1';
676  --tx_src_rdy_n <= '1';
677  tx_data <= (others => '1');
678  lcl_lnk_tx_nxt_state <= IDLE;
679  -- stat_tx_in_progress <= '0';
680  when IDLE =>
681  -- wait until FIFO has data and Aurora ready
682  -- PRIORITY ENCODER:
683  -- trig ==> daq ==> status
684  if tx_dst_rdy_n = '0' then
685  if pkttp_ctr_tc = '0' then
686  if trg_fifo_epty = '0' then
687  lcl_lnk_tx_nxt_state <= SEND_TRIG_SOF;
688  else
689  lcl_lnk_tx_nxt_state <= IDLE;
690  end if;
691  else
692  if daq_fifo_epty = '0' then
693  lcl_lnk_tx_nxt_state <= SEND_DAQ_SOF;
694  else
695  if status_upd = '1' then
696  lcl_lnk_tx_nxt_state <= SEND_STATUS_SOF;
697  else
698  lcl_lnk_tx_nxt_state <= IDLE;
699  end if;
700  end if;
701  end if;
702  else
703  lcl_lnk_tx_nxt_state <= IDLE;
704  end if;
705  when SEND_TRIG_SOF =>
706  -- make sure trigger SOF is read
707  trg_fifo_re <= (not tx_dst_rdy_n) and (not trg_fifo_epty) and (not atrg_sof);
708  if ((not tx_dst_rdy_n) and atrg_sof) = '1' then
709  -- make sure SOF was read
710  tx_sof_n <= '0';
711  --tx_src_rdy_n <= '0';
712  lcl_lnk_tx_nxt_state <= SEND_TRIG_PAYLOADS;
713  tx_data <= TRG_SOF_VAL;-- insert trigger SOF value
714  else
715  -- wait otherwise
716  tx_sof_n <= '1';
717  --tx_src_rdy_n <= '1';
718  lcl_lnk_tx_nxt_state <=SEND_TRIG_SOF;
719  tx_data <= trg_fifo_do(15 downto 0);-- FIFO data
720  end if;
721  --tx_data <= trg_fifo_do(15 downto 0);
722  when SEND_TRIG_PAYLOADS =>
723  -- make sure the trigger payload is read until EOF
724  trg_fifo_re <= (not tx_dst_rdy_n) and (not trg_fifo_epty) and (not (atrg_eof and pkttp_ctr_tc));
725  --tx_src_rdy_n <= tx_dst_rdy_n or trg_fifo_epty;
726  if ((not tx_dst_rdy_n) and (atrg_eof and pkttp_ctr_tc)) = '1' then
727  -- make sure EOF was read
728  --tx_eof_n <= '0';--g
729  strg_eof <= '1';--n
730  lcl_lnk_tx_nxt_state <= SEND_TRIG_EOF;
731  else
732  -- keep reading otherwise
733  --tx_eof_n <= '1';--g
734  strg_eof <= '0';--n
735  lcl_lnk_tx_nxt_state <= SEND_TRIG_PAYLOADS;
736  end if;
737  tx_data <= trg_fifo_do(15 downto 0);
738  when SEND_TRIG_EOF =>
739  -- write EOF and counters for debug
740  --tx_eof_n <= '0';--n
741  tx_eof_n <= not (daq_pause(daq_pause'length-1) and (not daq_pause(daq_pause'length-2)));--n
742  -- current --------------------------
743  -- packet counter freezes
744  --pkttp_ctr_ld <= '1';-- use for pause
745  -------------------------------------
746  -- new -------------------------------
747  -- fixed trigger window, free running counter
748  -- do nothing, default sets pkttp_ctr_ld <= '0'
749  --------------------------------------
750  -- where do we go next? - send status if sent enough trigger packets and DAQ ZLT
751  if daq_pause(0) = '1' then
752  if daq_fifo_epty = '0' then
753  lcl_lnk_tx_nxt_state <= SEND_DAQ_SOF;
754  else
755  lcl_lnk_tx_nxt_state <= IDLE;
756  end if;
757  else
758  lcl_lnk_tx_nxt_state <= SEND_TRIG_EOF;
759  end if;
760  tx_data <= trgsof_ctr & trgeof_ctr;
761  when SEND_DAQ_SOF =>
762  -- make sure DAQ SOF is read
763  pkttp_ctr_ld <= '1';
764  daq_fifo_re <= (not tx_dst_rdy_n) and (not daq_fifo_epty) and (not daq_sof);
765  if ((not tx_dst_rdy_n) and daq_sof) = '1' then
766  tx_sof_n <= '0';
767  --tx_src_rdy_n <= '0';
768  trgpkt_ctr_en <= '1';
769  lcl_lnk_tx_nxt_state <= SEND_DAQ_PAYLOADS;
770  else
771  tx_sof_n <= '1';
772  --tx_src_rdy_n <= '1';
773  trgpkt_ctr_en <= '0';
774  lcl_lnk_tx_nxt_state <= SEND_DAQ_SOF;
775  end if;
776  tx_data <= daq_fifo_do(15 downto 0);
777  when SEND_DAQ_PAYLOADS =>
778  -- make sure the DAQ payload is read until EOF
779  pkttp_ctr_ld <= '1';
780  daq_fifo_re <= (not tx_dst_rdy_n) and (not daq_fifo_epty) and (not daq_eof);
781  --tx_src_rdy_n <= tx_dst_rdy_n or daq_fifo_epty;
782  --if ((not tx_dst_rdy_n) and daq_eof) = '1' then--g
783  tx_eof_n <= not (daq_eof and (not sts_pause(sts_pause'length-1)));
784  if ((not tx_dst_rdy_n) and daq_eof and sts_pause(0)) = '1' then --n
785  --tx_eof_n <= '0';--g
786  if trgpkt_ctr_tc = '1' then --g
787  lcl_lnk_tx_nxt_state <= SEND_STATUS_SOF;
788  else
789  lcl_lnk_tx_nxt_state <= IDLE;
790  end if;
791  else
792  --tx_eof_n <= '1';--g
793  lcl_lnk_tx_nxt_state <= SEND_DAQ_PAYLOADS;
794  end if;
795  tx_data <= daq_fifo_do(15 downto 0);
796  when SEND_STATUS_SOF =>
797  -- send start of frame (SOF)
798  pkttp_ctr_ld <= '1';
799  trgpkt_ctr_ld <= '1';
800  sts_sof <= '1';
801  if ((not tx_dst_rdy_n) and sts_sof_q) = '1' then
802  tx_sof_n <= '0';
803  lcl_lnk_tx_nxt_state <= SEND_STATUS_PAYLOADS;
804  else
805  tx_sof_n <= '1';
806  lcl_lnk_tx_nxt_state <= SEND_STATUS_SOF;
807  end if;
808  tx_data <= sts_data;
809  when SEND_STATUS_PAYLOADS =>
810  stat_tx_in_progress <= '1';
811  pkttp_ctr_ld <= '1';
812  trgpkt_ctr_ld <= '1';
813  stspkt_ctr_ld <= '0';
814  --tx_eof_n <= not (stspkt_ctr_tc and (not idl_pause(idl_pause'length-1)));-- sts_eof;--gish
815  tx_eof_n <= not (stspkt_ctr_tc and (not OR_REDUCE(idl_pause)));--n
816  stspkt_ctr_en <= (not tx_dst_rdy_n) and (not stspkt_ctr_tc);
817  sts_eof <= (not tx_dst_rdy_n) and stspkt_ctr_tc;
818  if idl_pause(0) = '1' then --n
819  lcl_lnk_tx_nxt_state <= IDLE;
820  else
821  lcl_lnk_tx_nxt_state <= SEND_STATUS_PAYLOADS;
822  end if;
823  tx_data <= sts_data;
824  when others =>
825  lcl_lnk_tx_nxt_state <= IDLE;
826  end case;
827  end process;
828 
829  --------------------------------------------------------------------------
830  -- Synchronous portion of local link transmit state machine.
831  --------------------------------------------------------------------------
832  ll_tx_fsm_s : process(sys_clk)
833  begin
834  if (sys_clk'event and sys_clk = '1') then
835  if b2tt_runreset = '1' then
836  lcl_lnk_tx_state <= RESETTING;
837  else
838  lcl_lnk_tx_state <= lcl_lnk_tx_nxt_state;
839  end if;
840  end if;
841  end process;
842 
843  ------------------------------------------------------------------
844  -- Generate the local link signals. Make something sensible of
845  -- the state machine outputs.
846  ------------------------------------------------------------------
847  ll_tx_pcs : process(sys_clk)
848  begin
849  if (sys_clk'event and sys_clk = '1') then
850  --use atrg_sof to inject trigger SOF word, delay read enable signals
851  -- so FIFO out if valid
853  --tx_src_rdy_n <= not (trg_fifo_re or daq_fifo_re);
854  --tx_src_rdy_n <= not (atrg_sof or trg_fifo_re or daq_fifo_re);
855  tx_src_rdy_n <= not (atrg_sof
856  or strg_eof
857  or trg_fifo_re
858  or daq_fifo_re
859  or (sts_sof and (not sts_sof_q))
860  or stspkt_ctr_en);
861  end if;
862  end process;
863 
864  ------------------------------------------------------------------
865  -- Recieve data from the Aurora lane and write to the run control
866  -- interface.
867  ------------------------------------------------------------------
868  ll_rx_pcs : process(sys_clk)
869  begin
870  if (sys_clk'event and sys_clk = '1') then
871  --?just pass it through for now
872  -- rx_dst_rdy_n <= rcl_dst_rdy_n;
873  -- rcl_sof_n <= rx_sof_n;
874  -- rcl_eof_n <= rx_eof_n;
875  rcl_src_rdy_n <= rx_src_rdy_n;
876  rcl_data <= rx_data;
877  end if;
878  end process;
879 
880 end behave;
881 --------------------------------------------------------------------------------------------------------
882 
conc_intfc_pkg
Definition: conc_intfc_pkg.vhd:24
conc_intfc
Definition: conc_intfc.vhd:42
trig_chan_calc
Definition: trig_chan_calc.vhd:43