behave Architecture Reference

Processes
exttrg_pcs	( tdc_clk )
b2tt_pcs	( sys_clk )
trg_wr_pcs	( tdc_clk )
trg_rd_pcs	( sys_clk )
daq_wr_pcs	( sys_clk )
	make sure afull provides enough delay
daq_rd_pcs	( sys_clk )
status_wr_pcs	( sys_clk , stspkt_ctr_en , status_upd )
packet_pcs	( sys_clk )
ll_tx_fsm_a	( lcl_lnk_tx_state , tx_dst_rdy_n , pkttp_ctr_tc , trg_fifo_epty , daq_fifo_epty , atrg_sof , atrg_eof , daq_sof , daq_eof , trgpkt_ctr_tc , trg_fifo_do , daq_fifo_do , daq_pause( 0 ) , stspkt_ctr_tc , sts_data , sts_pause , idl_pause , sts_eof , status_upd , trgsof_ctr , sts_sof_q )
ll_tx_fsm_s	( sys_clk )
ll_tx_pcs	( sys_clk )
	delaying this makes invalid local link signal because DST_RDY_N is zero delay
ll_rx_pcs	( sys_clk )

Components
tdc
time_order
trig_chan_calc	<Entity trig_chan_calc>
trig_fifo
daq_fifo

Types
tx_fsm_type	( RESETTING , IDLE , SEND_TRIG_SOF , SEND_TRIG_PAYLOADS , SEND_DAQ_SOF , SEND_DAQ_PAYLOADS , SEND_TRIG_EOF , SEND_STATUS_SOF , SEND_STATUS_PAYLOADS )
word_shift_type	array ( natural range <> ) of std_logic_vector ( 15 downto 0 )

Signals
exttrg_ctr	std_logic_vector ( 3 downto 0 ) := ( others = > ' 0 ' )
tdc_rden	std_logic_vector ( 1 to TDC_NASICS )
tdc_epty	std_logic_vector ( 1 to TDC_NASICS )
tdc_dout	tdc_dout_type
to_dst_we	std_logic
to_dout	std_logic_vector ( TO_WIDTH- 1 downto 0 )
to_valid	std_logic_vector ( 1 downto 0 )
trg_fifo_we	std_logic := ' 0 '
trg_fifo_di	std_logic_vector ( 17 downto 0 )
trg_fifo_re	std_logic
trg_fifo_do	std_logic_vector ( 17 downto 0 )
trg_fifo_afull	std_logic
trg_fifo_epty	std_logic
trg_fifo_aepty	std_logic
trg_fifo_full	std_logic
daq_fifo_we	std_logic := ' 0 '
daq_fifo_di	std_logic_vector ( 17 downto 0 )
daq_fifo_re	std_logic
daq_fifo_do	std_logic_vector ( 17 downto 0 )
daq_fifo_afull	std_logic
daq_fifo_epty	std_logic
daq_fifo_aepty	std_logic
daq_fifo_full	std_logic
axis_bit	std_logic
trg_ch	std_logic_vector ( 7 downto 0 )
trg_ch_valid	std_logic
strg_eof	std_logic
trg_valid	std_logic_vector ( 0 downto 0 )
trgsof_ctr	std_logic_vector ( 7 downto 0 )
trgeof_ctr	std_logic_vector ( 7 downto 0 )
zrlentrg	std_logic
ftrgtag	std_logic
daq_sof_d	std_logic
daq_eof_d	std_logic
daq_sof_q	std_logic_vector ( 1 downto 0 )
daq_eof_q	std_logic_vector ( 1 downto 0 )
daq_src_rdy_q	std_logic_vector ( 1 downto 0 )
daq_data_q	word_shift_type ( 1 downto 0 )
daq_valid	std_logic_vector ( 2 downto 0 )
daq_di_addr	std_logic_vector ( 2 downto 0 )
daq_pause	std_logic_vector ( 3 downto 0 )
sts_pause	std_logic_vector ( 1 downto 0 )
idl_pause	std_logic_vector ( 1 downto 0 )
pkttp_ctr_ld	std_logic
pkttp_ctr_tc	std_logic
pkttp_ctr	std_logic_vector ( PKTTP_CTRW- 1 downto 0 )
trgpkt_ctr_ld	std_logic
trgpkt_ctr_en	std_logic
trgpkt_ctr_tc	std_logic
trgpkt_ctr	std_logic_vector ( TGPKT_CTRW- 1 downto 0 )
stspkt_ctr_ld	std_logic
stspkt_ctr_en	std_logic
stspkt_ctr_tc	std_logic
stspkt_ctr	std_logic_vector ( STSPKT_CTRW- 1 downto 0 )
sts_sof	std_logic
sts_eof	std_logic
sts_sof_q	std_logic
status_regs_i	stat_reg_type
sts_data	std_logic_vector ( 15 downto 0 )
lcl_lnk_tx_state	tx_fsm_type := RESETTING
lcl_lnk_tx_nxt_state	tx_fsm_type
to_tdc	std_logic_vector ( TDC_TWIDTH downto 0 )
exttb_format	std_logic_vector ( 3 downto 0 ) := ( others = > ' 0 ' )

Instantiations
tdc_ins	tdc
tmodr_ins	time_order
trg_chan_ins	trig_chan_calc <Entity trig_chan_calc>
trig_fifo_ins	trig_fifo
daq_fifo_ins	daq_fifo

Aliases
to_ln	is to_dout ( 16 downto 13 )
to_ch	is to_dout ( 12 downto 9 )
trgtag	is b2tt_fifodata ( 47 downto 32 )
atrg_sof	is trg_fifo_do ( trg_fifo_do ' length- 1 )
atrg_eof	is trg_fifo_do ( trg_fifo_do ' length- 2 )
daq_sof	is daq_fifo_do ( daq_fifo_do ' length- 1 )
daq_eof	is daq_fifo_do ( daq_fifo_do ' length- 2 )

Detailed Description

Definition at line 95 of file conc_intfc.vhd.

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The documentation for this class was generated from the following file:

• conc_intfc/source/conc_intfc.vhd