Belle II KLM Scint Firmware  1
daq_gen_readout.vhd
1 library ieee;
2 use ieee.std_logic_1164.all;
3 use ieee.numeric_std.all;
4 use ieee.std_logic_unsigned.all;
5 
6 entity daq_gen_readout is
7  port(
8  clk : in std_logic;
9  reset : in std_logic;
10 
11  tx_dst_rdy_n : in std_logic;
12  tx_src_rdy_n : out std_logic;
13  tx_sof_n : out std_logic;
14  tx_eof_n : out std_logic;
15  tx_d : out std_logic_vector(15 downto 0);
16 
17  qt_fifo_rd_en : out std_logic;
18  qt_fifo_rd_d : in std_logic_vector(17 downto 0);
19  qt_fifo_empty : in std_logic;
20  qt_fifo_evt_rdy : in std_logic
21  );
22 end daq_gen_readout;
23 
24 architecture multi_trig of daq_gen_readout is
25 
26  type lls_fsm_type is (SOFS,PAYLOADS,EOFS);
27 
28  signal ll_fsm_cs_t : lls_fsm_type := SOFS;
29 
30  signal qt_fifo_evt_rdy_i : std_logic_vector(5 downto 0):="000000";
31  signal tx_force_sof_eof : std_logic:='0';
32 
33 begin
34 
35 --------------------------------------------------------------------------------------------------------
36 -- Component instantiations
37 --------------------------------------------------------------------------------------------------------
38 
39 
40 --------------------------------------------------------------------------------------------------------
41 -- Concurrent statements
42 --------------------------------------------------------------------------------------------------------
43 
44 --------------------------------------------------------------------------------------------------------
45 -- Synchronous processes
46 --------------------------------------------------------------------------------------------------------
47  process(clk)
48  begin
49  if rising_edge(clk) then
50  if reset = '1' then
51  qt_fifo_evt_rdy_i <= (others => '0');
52  else
53  qt_fifo_evt_rdy_i <= qt_fifo_evt_rdy_i(4 downto 0) & qt_fifo_evt_rdy;
54  end if;
55  end if;
56 
57  end process;
58 
59  -------------------------------------------------------------
60  -- State machine to generate local link signals.
61  -------------------------------------------------------------
62  ll_fsm : process(clk)
63  begin
64  if (clk'event and clk='1') then
65  if reset = '1' then
66  tx_force_sof_eof<='1';
67  tx_src_rdy_n <= '1';
68  ll_fsm_cs_t <= SOFS;
69  else
70 
71  case ll_fsm_cs_t is
72  when SOFS =>
73  -- wait for the packet counters, send SOF
74  if (qt_fifo_evt_rdy_i(5 downto 4)="01" and tx_dst_rdy_n='0') then
75  tx_force_sof_eof<='1';
76  qt_fifo_rd_en<='1';
77  ll_fsm_cs_t <= PAYLOADS;
78  else
79  -- idle
80  tx_force_sof_eof<='1';
81  qt_fifo_rd_en<='0';
82  tx_src_rdy_n <= '1';
83  ll_fsm_cs_t <= SOFS;
84  end if;
85  when PAYLOADS =>
86  if (qt_fifo_empty='1') then
87  qt_fifo_rd_en<='0';
88  tx_force_sof_eof<='1';
89  tx_src_rdy_n <= '1';
90  ll_fsm_cs_t <= EOFS;
91  else
92  tx_force_sof_eof<='0';
93  qt_fifo_rd_en<='1';
94  tx_src_rdy_n <= tx_dst_rdy_n;
95  ll_fsm_cs_t <= PAYLOADS;
96  end if;
97  when EOFS =>
98  if tx_dst_rdy_n = '0' then
99  ll_fsm_cs_t <= SOFS;
100  else
101  ll_fsm_cs_t <= EOFS;
102  end if;
103 
104  when others =>
105  tx_force_sof_eof<='1';
106  tx_src_rdy_n <= '1';
107  ll_fsm_cs_t <= SOFS;
108  end case;
109  end if;
110  end if;
111  end process;
112 
113  -------------------------------------------------------------
114  -- Generat Local Link logic output.
115  -------------------------------------------------------------
116  tx_d<=qt_fifo_rd_d(15 downto 0);
117  tx_sof_n<=qt_fifo_rd_d(16) when tx_force_sof_eof='0' else '1';
118  tx_eof_n<=qt_fifo_rd_d(17) when tx_force_sof_eof='0' else '1';
119 
120 
121 
122 end multi_trig;
123 
daq_gen_readout
Definition: daq_gen_readout.vhd:6