behave Architecture Reference

Processes
PROCESS_175	( sysclk )
sysin_regs	( sys_clk_ib )
sout_regs	( sys_clk_ib )

Components
IBUFDS
IBUF
OBUF
timing_ctrl	<Entity timing_ctrl>
klm_aurora_intfc	<Entity klm_aurora_intfc>
conc_intfc	<Entity conc_intfc>
sfp_stat_ctrl	<Entity sfp_stat_ctrl>

Constants
NUM_ATBS	integer := 5
REFCLKSEL	std_logic_vector ( 2 downto 0 ) := " 000 "

Signals
mgtclk0_i	std_logic
mgtclk1_i	std_logic
mgtrxp_i	std_logic
mgtrxn_i	std_logic
mgttxp_i	std_logic
mgttxn_i	std_logic
mgttxfault_i	std_logic_vector ( 1 to NUM_GTS )
mgtmod0_i	std_logic_vector ( 1 to NUM_GTS )
mgtlos_i	std_logic_vector ( 1 to NUM_GTS )
mgttxdis_i	std_logic_vector ( 1 to NUM_GTS )
mgtmod2_i	std_logic_vector ( 1 to NUM_GTS )
mgtmod1_i	std_logic_vector ( 1 to NUM_GTS )
target_tb_i	tb_vec_type
control_fake_i	std_logic := ' 0 '
status_fake_i	std_logic := ' 0 '
sys_clk_ib	std_logic
sys_clk2x_ib	std_logic
mgttxfault_qi	std_logic_vector ( 1 to NUM_GTS )
mgtmod0_qi	std_logic_vector ( 1 to NUM_GTS )
mgtlos_qi	std_logic_vector ( 1 to NUM_GTS )
mgttxdis_iq	std_logic_vector ( 1 to NUM_GTS )
mgtmod2_iq	std_logic_vector ( 1 to NUM_GTS )
mgtmod1_iq	std_logic_vector ( 1 to NUM_GTS )
b2tt_b2clkup_i	std_logic
b2tt_ctime_i	std_logic_vector ( 26 downto 0 )
b2tt_divclk1_i	std_logic_vector ( 1 downto 0 )
b2tt_divclk2_i	std_logic_vector ( 1 downto 0 )
b2tt_runreset_i	std_logic
b2tt_gtpreset_i	std_logic
b2tt_b2ttver_i	std_logic_vector ( 15 downto 0 )
b2tt_fifordy_i	std_logic
b2tt_fifodata_i	std_logic_vector ( 95 downto 0 )
b2tt_exprun_i	std_logic_vector ( 31 downto 0 )
b2tt_frame_i	std_logic
b2tt_frame9_i	std_logic
b2tt_trgtag_i	std_logic_vector ( 31 downto 0 )
b2tt_fifonext_i	std_logic
b2tt_ctime_or	std_logic
rx_src_rdy_n	std_logic
rx_data	std_logic_vector ( 15 downto 0 )
tx_dst_rdy_n	std_logic
tx_sof_n	std_logic
tx_eof_n	std_logic
tx_src_rdy_n	std_logic
tx_data	std_logic_vector ( 15 downto 0 )
tdc_clk	std_logic
tdc_ce	std_logic_vector ( 1 to 5 )
b2tt_frame2x	std_logic_vector ( 1 to 3 )
b2tt_runreset2x	std_logic_vector ( 1 to 3 )
b2tt_runreset_tdc	std_logic_vector ( 1 to 3 )
status_regs	stat_reg_type
ctrl_regs	ctrl_reg_type
daq_dst_rdy_n	std_logic
daq_sof_n	std_logic
daq_eof_n	std_logic
daq_src_rdy_n	std_logic
daq_data	std_logic_vector ( 15 downto 0 )
inttb	tb_vec_type

Attributes
keep	string
keep	b2tt_trgtag_i : signal is " true "

Instantiations
mgtclk0_inst	ibufds
mgtclk1_inst	ibufds
atb_ibuf	ibuf
mgttxfault_ibuf	ibuf
mgtmod0_ibuf	ibuf
mgtlos_ibuf	ibuf
mgtrxp_ibuf	ibuf
mgtrxn_ibuf	ibuf
mgttxdis_obuf	obuf
mgtmod2_obuf	obuf
mgtmod1_obuf	obuf
mgttxp_obuf	obuf
mgttxn_obuf	obuf
tmg_ctrl_ins	timing_ctrl <Entity timing_ctrl>
aurora_ins	klm_aurora_intfc <Entity klm_aurora_intfc>
conc_intfc_ins	conc_intfc <Entity conc_intfc>
daq_gen_ins	daq_gen_readout <Entity daq_gen_readout>
sfp_stat_ctrl_ins	sfp_stat_ctrl <Entity sfp_stat_ctrl>

Aliases
NUM_ASICS	is TDC_NASICS

Detailed Description

Definition at line 145 of file klm_intfc.vhd.

Member Data Documentation

daq_gen_ins

daq_gen_ins daq_gen_readout

Instantiation

A packet is an entire trigger. Must be synced with b2tt trigger/fifo read.

Definition at line 676 of file klm_intfc.vhd.

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The documentation for this class was generated from the following file:

• klm_scrod/source/klm_intfc.vhd