Belle II KLM Scint Firmware  1
KLMReadoutCtrl Entity Reference
Inheritance diagram for KLMReadoutCtrl:
KLMTrigBitsProc WaveformReadout KLMReadoutTrg SamplingLgc SamplingMask fifo_cc KLMHitDataSerializer MeasurePeds PedestalWriter PedestalFetcher SingleBusProcessing CalculateROI fifo_cc klm_scint

Entities

behavioral  architecture
 

Libraries

ieee 
unisim 
work 

Use Clauses

std_logic_1164 
numeric_std 
std_logic_unsigned 
std_logic_misc 
vcomponents 
conc_intfc_pkg  Package <conc_intfc_pkg>
klm_scint_pkg  Package <klm_scint_pkg>
klm_scrod_pkg  Package <klm_scrod_pkg>
tdc_pkg 

Generics

T_DELAY_SELF_TRIG  integer := 4
FORCE_TRIG_BUF_DEPTH_g  integer := 5
FORCE_TRIG_WIDTH_g  integer := 8
POST_MUX_TRIG_BIT_BUFF_DEPTH_g  integer := 3

Ports

clk   in std_logic := ' 0 '
rst   in std_logic := ' 0 '
trg   in std_logic := ' 0 '
 b2tt signals
trgtag   in std_logic_vector ( 31 downto 0 ) := ( others = > ' 0 ' )
ctime   in std_logic_vector ( 26 downto 0 ) := ( others = > ' 0 ' )
vectrgbits   in tb_vec_type := ( others = > ( others = > ' 0 ' ) )
 trigger bits from all asics
qt_fifo_rd_en   in std_logic := ' 0 '
 daq data ports
qt_fifo_dout   out std_logic_vector ( 17 downto 0 ) := ( others = > ' 0 ' )
qt_fifo_empty   out std_logic := ' 1 '
qt_fifo_evt_rdy   out std_logic := ' 0 '
ScrodConfig   in KlmScrodConfigType := KlmScrodConfigZero
force_trig   in std_logic
sps_reset   in std_logic
scalers_reset   in std_logic := ' 0 '
 reset scalers for trigger bits
scalers_busy   out std_logic
 status ports TODO : pack it into a record e.g. ReadoutStatus
scalers_ch_arr   out slv32 ( 9 downto 0 ) := ( others = > ( others = > ' 0 ' ) )
qt_fifo_err_cnt   out std_logic_vector ( 15 downto 0 )
 tbfifo_cnt : out slv16(9 downto 0) := (others => (others => '0')); – debug
tbfifo_err_cnt   out slv16 ( 9 downto 0 )
trg_cnt   out std_logic_vector ( 15 downto 0 ) := ( others = > ' 0 ' )
full_proc_cnt   out std_logic_vector ( 15 downto 0 ) := ( others = > ' 0 ' )
simp_proc_cnt   out std_logic_vector ( 15 downto 0 ) := ( others = > ' 0 ' )
null_proc_cnt   out std_logic_vector ( 15 downto 0 ) := ( others = > ' 0 ' )
wave_stat   out waveform_stat_t
debug_wave_we   out std_logic_vector ( 1 downto 0 ) := ( others = > ' 0 ' )
debug_wave_din   out slv12 ( 1 downto 0 ) := ( others = > ( others = > ' 0 ' ) )
SPS_hist_rd_data   out slv16 ( 1 downto 0 ) := ( others = > ( others = > ' 0 ' ) )
RAM_IO   inout std_logic_vector ( 7 downto 0 ) := ( others = > ' 0 ' )
 debug FIXME : remove pedestal RAM access
RAM_WEb   out std_logic := ' 1 '
RAM_OEb   out std_logic := ' 1 '
RAM_ADDR   out std_logic_vector ( 21 downto 0 ) := ( others = > ' 1 ' )
BUSA_WR_ADDRCLR   out std_logic
 BusA signals.
BUSA_DO   in std_logic_vector ( 14 downto 0 ) := ( others = > ' 0 ' )
BUSA_RAMP   out std_logic := ' 0 '
BUSA_CLR   out std_logic := ' 0 '
BUSA_RD_COLSEL   out std_logic_vector ( 5 downto 0 ) := ( others = > ' 0 ' )
BUSA_RD_ENA   out std_logic := ' 0 '
BUSA_RD_ROWSEL   out std_logic_vector ( 2 downto 0 ) := ( others = > ' 0 ' )
BUSA_SAMPLESEL   out std_logic_vector ( 4 downto 0 ) := ( others = > ' 0 ' )
BUSA_SR_CLEAR   out std_logic := ' 0 '
BUSA_SR_SEL   out std_logic := ' 0 '
BUSB_WR_ADDRCLR   out std_logic
 BusB signals.
BUSB_DO   in std_logic_vector ( 14 downto 0 ) := ( others = > ' 0 ' )
BUSB_RAMP   out std_logic := ' 0 '
BUSB_CLR   out std_logic := ' 0 '
BUSB_RD_COLSEL   out std_logic_vector ( 5 downto 0 ) := ( others = > ' 0 ' )
BUSB_RD_ENA   out std_logic := ' 0 '
BUSB_RD_ROWSEL   out std_logic_vector ( 2 downto 0 ) := ( others = > ' 0 ' )
BUSB_SAMPLESEL   out std_logic_vector ( 4 downto 0 ) := ( others = > ' 0 ' )
BUSB_SR_CLEAR   out std_logic := ' 0 '
BUSB_SR_SEL   out std_logic := ' 0 '
WR1_ENA   out std_logic_vector ( 9 downto 0 )
 TargetX DC signals.
WR2_ENA   out std_logic_vector ( 9 downto 0 )
SSTIN_N   out std_logic_vector ( 9 downto 0 )
SSTIN_P   out std_logic_vector ( 9 downto 0 )
SAMPLESEL_ANY   out std_logic_vector ( 9 downto 0 ) := ( others = > ' 0 ' )
SR_CLOCK   out std_logic_vector ( 9 downto 0 ) := ( others = > ' 0 ' )
busy   out std_logic := ' 0 '

Detailed Description

This module both stores and sends primitive ("L0") triggers as soon as they are received. When a readout trigger is received, the stored primitive triggers are are checked for hits within the lookback window. If a hit is present, the associated analog-storage windows are masked off to prevent overwriting, then waveform digitization, readout, and processing are performed, and a DAQ packet containing feature-extracted data is sent to the Data Concentrator (via Aurora SFP). If no hit is present, then a 'null' packet is sent.

Modes
Trig type(set one high and other two to zero) use_ftsw_trig, use_force_trig, use_self_trig.
Measure Pedestals set measure_peds high, set trig type to forced, and initiate with force trig.
Measure SPS configure desired trigger type, then set sps_reset high before starting trigger (SPS ram always being filled, so just have to clear with sps_reset before trusting data).
Pedestal subtraction set ped_sub_ena on/off for any mode described above.

Definition at line 31 of file KLMReadoutCtrl.vhd.


The documentation for this class was generated from the following file: