behavioral Architecture Reference

Processes
latch_input_data	( clk , trg , trgtag , ctime , ScrodConfig , scalers_reset )
determine_where_ctime_wraps_around	( clk , rst , ctime , i_ctime , i_ctime_max )
buffer_the_reset_signal	( clk , rst )
TB_mode_mux	( clk , vectrgbits , force_trig , i_ScrodConfig.wave_config.use_force_trig , i_ScrodConfig.wave_config.force_trig_bits , i_ScrodConfig.wave_config.force_trig_asic , force_trig_sr , use_force_trig_sr )
self_trig_fsm	( clk , self_trig_asic )
KLMReadoutTrg_trig_mode_multiplexer	( clk , i_ScrodConfig.wave_config.use_ftsw_trig , i_trg , i_ctime , i_trgtag , self_trig )

Constants
ctime_zero	std_logic_vector ( 26 downto 0 ) := ( others = > ' 0 ' )

Types
arr_tb_vec_type	array ( natural range <> ) of tb_vec_type
	TB_mode_mux:
SELF_TRIG_STATE_t	( IDLE , TRIGGERING )
	self_trig_fsm:

Signals
i_trg	std_logic := ' 0 '
	latch_input_data:
i_trgtag	std_logic_vector ( 4 downto 0 ) := ( others = > ' 0 ' )
i_ctime	std_logic_vector ( 26 downto 0 ) := ( others = > ' 0 ' )
i_ScrodConfig	KlmScrodConfigType := KlmScrodConfigZero
i_scalers_reset	std_logic := ' 0 '
i_ctime_max	std_logic_vector ( 26 downto 0 ) := ( others = > ' 1 ' )
	determine_where_ctime_wraps_around:
wave_proc_rst	std_logic := ' 0 '
	buffer_the_reset_signal:
sampling_lgc_rst	std_logic := ' 0 '
tb_proc_rst	std_logic := ' 0 '
ro_trg_rst	std_logic := ' 0 '
i_vectrgbits	arr_tb_vec_type ( POST_MUX_TRIG_BIT_BUFF_DEPTH_g- 1 downto 0 ) := ( others = > ( others = > ( others = > ' 0 ' ) ) )
force_trig_sr	std_logic_vector ( FORCE_TRIG_BUF_DEPTH_g+ FORCE_TRIG_WIDTH_g- 1 downto 0 ) := ( others = > ' 0 ' )
use_force_trig_sr	std_logic_vector ( FORCE_TRIG_BUF_DEPTH_g- 1 downto 0 ) := ( others = > ' 0 ' )
self_trig_state	SELF_TRIG_STATE_t := IDLE
self_trig	std_logic := ' 0 '
ii_trg	std_logic := ' 0 '
	KLMReadoutTrg_trig_mode_multiplexer:
ii_trgtag	std_logic_vector ( 4 downto 0 ) := ( others = > ' 0 ' )
ii_ctime	std_logic_vector ( 26 downto 0 ) := ( others = > ' 0 ' )
trig	trig_info_type_0 := null_trig_info_t0
self_trig_asic	std_logic_vector ( 9 downto 0 ) := ( others = > ' 0 ' )
i_sca_busy	std_logic_vector ( 9 downto 0 ) := ( others = > ' 0 ' )
ro_busy_full	std_logic := ' 0 '
i_trg_proc_full_cnt	std_logic_vector ( 15 downto 0 ) := ( others = > ' 0 ' )
i_evt_rdy_full	std_logic := ' 0 '
ana_wr_ena_mask	TARGETX_analong_wr_ena_mask_t := null_TX_ana_wr_ena_mask
localtrg	std_logic := ' 0 '
ctime_trg	std_logic_vector ( 26 downto 0 ) := ( others = > ' 0 ' )
cur_win	std_logic_vector ( 8 downto 0 ) := ( others = > ' 0 ' )

Instantiations
klmtrigbitsproc_i	KLMTrigBitsProc <Entity KLMTrigBitsProc>
waveformreadout_i	WaveformReadout <Entity WaveformReadout>
readouttrg_i	KLMReadoutTrg <Entity KLMReadoutTrg>
targetx_samplinglgc_i	SamplingLgc <Entity SamplingLgc>

Detailed Description

Definition at line 132 of file KLMReadoutCtrl.vhd.

---

The documentation for this class was generated from the following file:

• klm_scint/source/KLMReadoutCtrl.vhd