KLMReadoutCtrl.vhd

library ieee;
   use ieee.std_logic_1164.all;
   use ieee.numeric_std.all;
   use ieee.std_logic_unsigned.all;
   use ieee.std_logic_misc.all;
library unisim;
   use unisim.vcomponents.all;
library work;
   use work.conc_intfc_pkg.all;
   use work.klm_scint_pkg.all;
   use work.klm_scrod_pkg.all;
   use work.tdc_pkg.all;



entity KLMReadoutCtrl is
   generic (
      T_DELAY_SELF_TRIG : integer := 4;
      FORCE_TRIG_BUF_DEPTH_g : integer := 5;
      FORCE_TRIG_WIDTH_g: integer := 8;
      POST_MUX_TRIG_BIT_BUFF_DEPTH_g : integer := 3
   );
   port (
      clk             : in  std_logic := '0';
      rst             : in  std_logic := '0';

      trg             : in  std_logic := '0';
      trgtag          : in  std_logic_vector(31 downto 0) := (others=>'0');
      ctime           : in  std_logic_vector(26 downto 0) := (others=>'0');


      vectrgbits      : in  tb_vec_type := (others => (others => '0')); -- array of trigger bits from TargetX

      qt_fifo_rd_en   : in  std_logic := '0';
      qt_fifo_dout    : out std_logic_vector (17 downto 0) := (others=>'0');
      qt_fifo_empty   : out std_logic := '1';
      qt_fifo_evt_rdy : out std_logic := '0';

      ScrodConfig     : in  KlmScrodConfigType := KlmScrodConfigZero;
      force_trig      : in std_logic;
      sps_reset       : in std_logic;

      scalers_reset   : in std_logic := '0';

      scalers_busy    : out std_logic;
      scalers_ch_arr  : out slv32(9 downto 0) := (others => (others => '0'));  -- one scaler per ASIC for given channel number
      qt_fifo_err_cnt : out std_logic_vector(15 downto 0); -- counter for daq data fifo overflows
      tbfifo_err_cnt  : out slv16(9 downto 0);    -- counter for trigger bits fifo overflows
      trg_cnt         : out std_logic_vector(15 downto 0) := (others => '0'); -- number of triggers received
      full_proc_cnt   : out std_logic_vector(15 downto 0) := (others => '0'); -- number of triggers processed
      simp_proc_cnt   : out std_logic_vector(15 downto 0) := (others => '0'); -- number of triggers processed
      null_proc_cnt   : out std_logic_vector(15 downto 0) := (others => '0'); -- number of triggers processed
      -- occ_err_cnt     : out std_logic_vector(15 downto 0) := (others => '0'); -- number of hits overflow counter
        -- status registers
      wave_stat       : out waveform_stat_t;
      debug_wave_we   : out std_logic_vector(1 downto 0) := (others => '0');
      debug_wave_din  : out slv12(1 downto 0) := (others => (others => '0'));
      SPS_hist_rd_data : out slv16(1 downto 0) := (others => (others => '0'));

      -- ctime_max       : out std_logic_vector(26 downto 0) := (others => '1'); -- where ctime acually wraps around

      RAM_IO          : inout std_logic_vector(7 downto 0) := (others => '0');
      RAM_WEb         : out std_logic := '1';
      RAM_OEb         : out std_logic := '1';
      RAM_ADDR        : out std_logic_vector(21 downto 0) := (others => '1');

      BUSA_WR_ADDRCLR : out std_logic;
      BUSA_DO         : in  std_logic_vector(14 downto 0) := (others => '0');
      BUSA_RAMP       : out std_logic := '0';
      BUSA_CLR        : out std_logic := '0';
      BUSA_RD_COLSEL  : out std_logic_vector(5 downto 0) := (others => '0');
      BUSA_RD_ENA     : out std_logic := '0';
      BUSA_RD_ROWSEL  : out std_logic_vector(2 downto 0) := (others => '0');
      BUSA_SAMPLESEL  : out std_logic_vector(4 downto 0) := (others => '0');
      BUSA_SR_CLEAR   : out std_logic := '0';
      BUSA_SR_SEL     : out std_logic := '0';


      BUSB_WR_ADDRCLR : out std_logic;
      BUSB_DO         : in  std_logic_vector(14 downto 0) := (others => '0');
      BUSB_RAMP       : out std_logic := '0';
      BUSB_CLR        : out std_logic := '0';
      BUSB_RD_COLSEL  : out std_logic_vector(5 downto 0) := (others => '0');
      BUSB_RD_ENA     : out std_logic := '0';
      BUSB_RD_ROWSEL  : out std_logic_vector(2 downto 0) := (others => '0');
      BUSB_SAMPLESEL  : out std_logic_vector(4 downto 0) := (others => '0');
      BUSB_SR_CLEAR   : out std_logic := '0';
      BUSB_SR_SEL     : out std_logic := '0';


      WR1_ENA         : out std_logic_vector(9 downto 0);
      WR2_ENA         : out std_logic_vector(9 downto 0);
      SSTIN_N         : out std_logic_vector(9 downto 0);
      SSTIN_P         : out std_logic_vector(9 downto 0);
      -- TDC_DONE        : in  std_logic_vector(9 downto 0) := (others => '0');
      SAMPLESEL_ANY   : out std_logic_vector(9 downto 0) := (others => '0');
      SR_CLOCK        : out std_logic_vector(9 downto 0) := (others => '0');

      busy            : out std_logic := '0'
   );
end KLMReadoutCtrl;




architecture behavioral of KLMReadoutCtrl is

-- SYNCHRONOUS SIGNALS BY PROCESS WHICH DRIVES THEM
    signal i_trg           : std_logic := '0';
    signal i_trgtag        : std_logic_vector(4 downto 0) := (others => '0');
    signal i_ctime         : std_logic_vector(26 downto 0) := (others => '0');
    signal i_ScrodConfig   : KlmScrodConfigType := KlmScrodConfigZero;
    signal i_scalers_reset : std_logic := '0';
    
    signal i_ctime_max       : std_logic_vector(26 downto 0) := (others => '1');
    constant ctime_zero      : std_logic_vector(26 downto 0) := (others => '0');
    
    signal wave_proc_rst : std_logic := '0';
    signal sampling_lgc_rst : std_logic := '0';
    signal tb_proc_rst : std_logic := '0';
    signal ro_trg_rst : std_logic := '0';
    
    type arr_tb_vec_type is array (natural range <>) of tb_vec_type;
    signal i_vectrgbits      : arr_tb_vec_type(POST_MUX_TRIG_BIT_BUFF_DEPTH_g - 1 downto 0) := (others=>(others => (others => '0')));
    signal force_trig_sr     : std_logic_vector(FORCE_TRIG_BUF_DEPTH_g + FORCE_TRIG_WIDTH_g - 1 downto 0) := (others=>'0');
    signal use_force_trig_sr : std_logic_vector(FORCE_TRIG_BUF_DEPTH_g - 1 downto 0) := (others=>'0');
    
    type SELF_TRIG_STATE_t is (IDLE, TRIGGERING);
    signal self_trig_state : SELF_TRIG_STATE_t := IDLE;
    signal self_trig        : std_logic := '0';
    
    signal ii_trg        : std_logic := '0';
    signal ii_trgtag      : std_logic_vector(4 downto 0) := (others => '0');
    signal ii_ctime      : std_logic_vector(26 downto 0) := (others => '0');


    
-- SIGNALS DRIVEN BY INSTANTIATED ENTITIES
    -- TrigBitsProc_10x_i :
    signal trig : trig_info_type_0 := null_trig_info_t0;
    signal self_trig_asic : std_logic_vector(9 downto 0) := (others => '0');
    signal i_sca_busy      : std_logic_vector(9 downto 0) := (others => '0');
    
       
    -- WaveformReadout_i :
    signal ro_busy_full   : std_logic := '0';
    signal i_trg_proc_full_cnt : std_logic_vector (15 downto 0)   := (others => '0');
    signal i_evt_rdy_full   : std_logic := '0';
    signal ana_wr_ena_mask : TARGETX_analong_wr_ena_mask_t := null_TX_ana_wr_ena_mask;
    
    
    -- ReadoutTrg_i :
    signal localtrg     : std_logic := '0';
    signal ctime_trg     : std_logic_vector(26 downto 0) := (others => '0');
    
    -- TargetX_SamplingLgc_i :
    signal cur_win               : std_logic_vector(8 downto 0) := (others => '0');


-- ASYNCHRONOUSLY DRIVEN SIGNALS


begin




--------------------- ASYNCHRONOUS LOGIC ---------------------------------------------
    scalers_busy <= or_reduce(i_sca_busy);
    busy <= ro_busy_full;
    trig.ctime <= ctime_trg(15 downto 0);
    



--------------------- SYNCHRONOUS LOGIC ---------------------------------------------
    latch_input_data: process(clk, trg, trgtag, ctime, ScrodConfig, scalers_reset)
    begin
       if rising_edge(clk) then
          i_trg           <= trg;
          i_trgtag        <= trgtag(4 downto 0);
          i_ctime         <= ctime;
          i_ScrodConfig   <= ScrodConfig;
          i_scalers_reset <= scalers_reset;
       end if;
    end process;



    determine_where_ctime_wraps_around: process(clk, rst, ctime, i_ctime, i_ctime_max)
    begin
       if rising_edge(clk) then
          if rst = '1' then
             i_ctime_max <= (others => '1');
          else
             if ctime = ctime_zero and i_ctime > ctime_zero then
                i_ctime_max <= i_ctime;
             end if;
             -- ctime_max <= i_ctime_max;
          end if;
       end if;
    end process;
    


    buffer_the_reset_signal: process(clk, rst)
    begin
       if rising_edge(clk) then
          wave_proc_rst <= rst;
          sampling_lgc_rst <= rst;
          tb_proc_rst <= rst;
          ro_trg_rst <= rst;
       end if;
    end process;


    TB_mode_mux: process(clk, vectrgbits, force_trig,
            i_ScrodConfig.wave_config.use_force_trig,
            i_ScrodConfig.wave_config.force_trig_bits,
            i_ScrodConfig.wave_config.force_trig_asic,
            force_trig_sr, use_force_trig_sr)
    begin
        if rising_edge(clk) then
            if force_trig = '1' then
                force_trig_sr(force_trig_sr'left downto FORCE_TRIG_WIDTH_g) <= (others=>'0');
                force_trig_sr(FORCE_TRIG_WIDTH_g - 1 downto 0) <= (others=>'1');
            else
                force_trig_sr <= force_trig_sr(force_trig_sr'left - 1 downto 0) & '0';
            end if;
            use_force_trig_sr <= use_force_trig_sr(use_force_trig_sr'left - 1 downto 0) & i_ScrodConfig.wave_config.use_force_trig;
            i_vectrgbits(i_vectrgbits'left downto 1) <= i_vectrgbits(i_vectrgbits'left - 1 downto 0);
            if use_force_trig_sr(use_force_trig_sr'left) = '1' then
                if force_trig_sr(force_trig_sr'left) = '1' then
                    i_vectrgbits(0)(i_ScrodConfig.wave_config.force_trig_asic(0) + 1) <= i_ScrodConfig.wave_config.force_trig_bits;
                    i_vectrgbits(0)(i_ScrodConfig.wave_config.force_trig_asic(1) + 6) <= i_ScrodConfig.wave_config.force_trig_bits;
                else
                    i_vectrgbits(0) <= (others=>(others=>'0'));
                end if;
            else
                i_vectrgbits(0) <= vectrgbits; 
            end if;
        end if;
    end process;



    self_trig_fsm: process(clk, self_trig_asic)
        variable count : integer range 0 to T_DELAY_SELF_TRIG := 0;
    begin
        if rising_edge(clk) then
            case self_trig_state is
                when IDLE =>
                    self_trig <= '0';
                    count := 0;
                    if or_reduce(self_trig_asic) = '1' then
                        self_trig_state <= TRIGGERING;
                    end if;

                when TRIGGERING =>
                    if count = T_DELAY_SELF_TRIG then
                        self_trig <= not i_ScrodConfig.wave_config.use_ftsw_trig;
                        self_trig_state <= IDLE;
                    else
                        count := count + 1;
                        self_trig_state <= TRIGGERING;
                    end if;

            end case;
        end if;    
    end process;



    KLMReadoutTrg_trig_mode_multiplexer: process(clk, i_ScrodConfig.wave_config.use_ftsw_trig,
                                                 i_trg, i_ctime, i_trgtag, self_trig)
    begin
        if rising_edge(clk) then
            
            ii_ctime <= i_ctime;
            ii_trgtag <= i_trgtag;
            if i_ScrodConfig.wave_config.use_ftsw_trig = '1' then
                ii_trg <= i_trg;
            else
                ii_trg <= self_trig;
            end if;
        end if;
    end process;


    
    
 --------------------- MODULE INSTANTIATIONS ---------------------------------------------
    
    TrigBitsProc_10x_i: for iAsic in 1 to 10 generate
       KLMTrigBitsProc_i : entity work.KLMTrigBitsProc
       port map(
          clk            => clk,
          rst            => tb_proc_rst,

          -- inputs
          tb             => i_vectrgbits(i_vectrgbits'left)(iAsic),

          ctime          => i_ctime,
          cur_win        => cur_win,
          -- ro_busy        => ro_busy_full,

          localtrg       => localtrg,
          ctime_trg      => ctime_trg,

          -- hit_ren        => i_hit_ren(iAsic-1), -- hit read enable
          sca_rst        => i_scalers_reset,
          sca_cnt_max    => i_ScrodConfig.TBScalersPeriod,

          -- configuration
          asic_on        => i_ScrodConfig.TxProcMask(iAsic-1),
          lookback       => i_ScrodConfig.TBLookBack,
          lookback_width => i_ScrodConfig.TBLookBackWidth,
          ctime_max      => i_ctime_max,

          -- outputs
          hit_bits       => trig.bits(iAsic-1),
          hit_win        => trig.wr_time(iAsic-1),
          is_hit         => trig.mask(iAsic-1),
          -- tbfifo_drdy    => tbfifo_drdy(iAsic-1),
          self_trig      => self_trig_asic(iAsic-1),

          -- status
          sca_busy       => i_sca_busy(iAsic-1),
          -- fifo_cnt       => i_tbfifo_cnt(iAsic-1),
          scalers_cnt    => scalers_ch_arr(iAsic-1),
          fifo_full_cnt  => tbfifo_err_cnt(iAsic-1)
       );
    end generate;


    WaveformReadout_i : entity work.WaveformReadout
    port map (
         clk                => clk,
         busy               => ro_busy_full,
         b2tt_runreset      => wave_proc_rst,
         trig               => trig,
         ana_wr_ena_mask    => ana_wr_ena_mask,
         localtrg           => localtrg,
         force_trig         => force_trig,
         sps_reset          => sps_reset,
         cur_win            => cur_win,
         qt_fifo_rd_en      => qt_fifo_rd_en,
         qt_fifo_dout       => qt_fifo_dout,
         qt_fifo_empty      => qt_fifo_empty,
         qt_fifo_err_cnt    => qt_fifo_err_cnt,
         qt_fifo_evt_rdy    => qt_fifo_evt_rdy,
         full_proc_cnt      => full_proc_cnt,
         simp_proc_cnt      => simp_proc_cnt,
         null_proc_cnt      => null_proc_cnt,
         RAM_IO             => RAM_IO,
         RAM_WEb            => RAM_WEb,
         RAM_OEb            => RAM_OEb,
         RAM_ADDR           => RAM_ADDR,
         BUSA_DO            => BUSA_DO,
         BUSA_RAMP          => BUSA_RAMP,
         BUSA_CLR           => BUSA_CLR,
         BUSA_RD_COLSEL     => BUSA_RD_COLSEL,
         BUSA_RD_ENA        => BUSA_RD_ENA,
         BUSA_RD_ROWSEL     => BUSA_RD_ROWSEL,
         BUSA_SAMPLESEL     => BUSA_SAMPLESEL,
         BUSA_SR_CLEAR      => BUSA_SR_CLEAR,
         BUSA_SR_SEL        => BUSA_SR_SEL,
         BUSB_DO            => BUSB_DO,
         BUSB_RAMP          => BUSB_RAMP,
         BUSB_CLR           => BUSB_CLR,
         BUSB_RD_COLSEL     => BUSB_RD_COLSEL,
         BUSB_RD_ENA        => BUSB_RD_ENA,
         BUSB_RD_ROWSEL     => BUSB_RD_ROWSEL,
         BUSB_SAMPLESEL     => BUSB_SAMPLESEL,
         BUSB_SR_CLEAR      => BUSB_SR_CLEAR,
         BUSB_SR_SEL        => BUSB_SR_SEL,
         SAMPLESEL_ANY      => SAMPLESEL_ANY,
         SR_CLOCK           => SR_CLOCK,
         wave_config        => i_ScrodConfig.wave_config,
         wave_stat          => wave_stat,
         debug_wave_we      => debug_wave_we,
         debug_wave_din     => debug_wave_din,
         SPS_hist_rd_data   => SPS_hist_rd_data
    );


   ReadoutTrg_i : entity work.KLMReadoutTrg
   port map(
      clk          => clk,
      rst          => ro_trg_rst,

      trg          => ii_trg,
      ctime        => ii_ctime,
      trgtag       => ii_trgtag,
      readout_busy => ro_busy_full,

      localtrg     => localtrg,
      ctime_trg    => ctime_trg,
      -- trgtag_trg   => trgtag_trg,

      trg_cnt      => trg_cnt
   );

 

    TargetX_SamplingLgc_i : entity work.SamplingLgc
    port map (
        clk             => clk,
        reset           => sampling_lgc_rst,
        ana_wr_ena_mask => ana_wr_ena_mask,
        cur_win         => cur_win,
        BUSA_WR_ADDRCLR => BUSA_WR_ADDRCLR,
        BUSB_WR_ADDRCLR => BUSB_WR_ADDRCLR,
        WR1_ENA         => WR1_ENA,
        WR2_ENA         => WR2_ENA,
        SSTIN_N         => SSTIN_N,
        SSTIN_P         => SSTIN_P
    );
        


        
end behavioral;