Belle II KLM Scint Firmware  1
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KLMReadoutTrg.vhd
1 library ieee;
2  use ieee.std_logic_1164.all;
3  use ieee.numeric_std.all;
4  use ieee.std_logic_unsigned.all;
5  use ieee.std_logic_misc.all;
6 library work;
7  use work.klm_scint_pkg.all;
8 
12 
13 entity KLMReadoutTrg is
14  port (
15  clk : in std_logic;
16  rst : in std_logic;
17 
18  trg : in std_logic;
19  ctime : in std_logic_vector(26 downto 0);
20  trgtag : in std_logic_vector(4 downto 0);
21  readout_busy : in std_logic;
22 
23  localtrg : out std_logic;
24  ctime_trg : out std_logic_vector(26 downto 0);
25  -- trgtag_trg : out std_logic_vector( 3 downto 0);
26 
27  trg_cnt : out std_logic_vector(15 downto 0)
28  );
29 end entity KLMReadoutTrg;
30 
31 architecture behav of KLMReadoutTrg is
32 
33  signal i_localtrg : std_logic := '0';
34 
35  --- trigger fifo signals
36  signal i_trgfifo_din : std_logic_vector(31 downto 0);
37  signal i_trgfifo_wen : std_logic;
38  signal i_trgfifo_ren : std_logic;
39  signal i_trgfifo_dout : std_logic_vector(31 downto 0);
40  -- signal i_trgfifo_full : std_logic;
41  signal i_trgfifo_empty : std_logic;
42 
43  -- counters
44  signal i_trg_cnt : std_logic_vector(15 downto 0) := (others => '0');
45 
46 
47 begin
48 
49  ------------------------------------------------
50  --- FIFO for TRG data
51  ------------------------------------------------
52  trgfifo_i : entity work.fifo_cc
53  generic map(
54  DATA_WIDTH => 32,
55  DEPTH => 8
56  )
57  port map (
58  clk => clk,
59  rst => rst,
60  din => i_trgfifo_din,
61  wen => i_trgfifo_wen,
62  ren => i_trgfifo_ren,
63  dout => i_trgfifo_dout,
64  full => open,
65  empty => i_trgfifo_empty
66  );
67 
68  i_trgfifo_ren <= i_localtrg;
69  i_trgfifo_din(26 downto 0) <= ctime;
70  i_trgfifo_din(31 downto 27) <= trgtag(4 downto 0);
71  i_trgfifo_wen <= trg;
72 
73  process (clk)
74  begin
75  if rising_edge (clk) then
76  if rst = '1' then
77  ctime_trg <= (others => '0');
78  -- trgtag_trg <= (others => '0');
79  else
80  i_localtrg <= '0';
81  if i_trgfifo_empty = '0' and readout_busy = '0' and i_localtrg = '0' then
82  i_localtrg <= '1';
83  ctime_trg <= i_trgfifo_dout(26 downto 0);
84  -- trgtag_trg <= i_trgfifo_dout(30 downto 27);
85  end if;
86  end if;
87  end if;
88  end process;
89  localtrg <= i_localtrg;
90 
91  ------------------------------------------------
92 
93  ------------------------------------------------
94  -- count incomming triggers
95  ------------------------------------------------
96  TRGCNT_PROC : process(clk, rst)
97  begin
98  if rst = '1' then
99  i_trg_cnt <= (others => '0');
100  elsif rising_edge(clk) then
101  if trg = '1' then
102  i_trg_cnt <= i_trg_cnt + 1;
103  end if;
104  end if;
105  end process TRGCNT_PROC;
106 
107  trg_cnt <= i_trg_cnt;
108  ------------------------------------------------
109 
110 end behav;
Definition: mem.vhd:103