fifo_cc Entity Reference

Inheritance diagram for fifo_cc:

Entities
fifo_cc_arch	architecture

Libraries
ieee

Use Clauses
std_logic_1164
std_logic_unsigned

Generics
DATA_WIDTH	natural := 16
DEPTH	natural := 5

Ports
clk	in std_logic
rst	in std_logic
din	in std_logic_vector ( DATA_WIDTH- 1 downto 0 )
wen	in std_logic
ren	in std_logic
dout	out std_logic_vector ( DATA_WIDTH- 1 downto 0 )
full	out std_logic
empty	out std_logic

Detailed Description

Definition at line 103 of file mem.vhd.

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The documentation for this class was generated from the following file:

• klm_scint/source/mem.vhd