KLMTrigBitsProc.vhd

library ieee;
   use ieee.std_logic_1164.all;
   use ieee.numeric_std.all;
   use ieee.std_logic_unsigned.all;
   use ieee.std_logic_misc.all;
library work;
   use work.conc_intfc_pkg.all;
   use work.klm_scint_pkg.all;
   use work.klm_scrod_pkg.all;


entity KLMTrigBitsProc is
    generic(
        CUR_WIN_LATENCY_g : integer := 5;  -- time between raw TB and TB latch logic
        CHECK_AND_READ_TIME_g : integer := 6;
        TB_LATCH_DELAY_g : integer := 4 -- time for tb's to mature
    );
   port(
      clk            : in std_logic;
      rst            : in std_logic;
                
      -- inputs
      tb             : in std_logic_vector(4 downto 0);  -- trigger bits from ASIC
                   
      ctime          : in std_logic_vector(26 downto 0); -- current ctime
      cur_win        : in std_logic_vector(8 downto 0);
      -- ro_busy        : in std_logic;

      localtrg       : in std_logic;                     -- trigger is readout from trgfifo
      ctime_trg      : in std_logic_vector(26 downto 0); -- ctime of the trigger
                   
      -- hit_ren        : in std_logic;                     -- read hit data from fifo
      sca_rst        : in std_logic;                     -- reset tb scalers
      sca_cnt_max    : in std_logic_vector(7 downto 0);  -- period to measure scalers
                   
      -- configuration 
      asic_on        : in std_logic;                     -- enable processing data for this specific asic
      lookback       : in std_logic_vector(15 downto 0); -- position in time of the lookback window
      lookback_width : in std_logic_vector(15 downto 0); -- width of the lookback window
      ctime_max      : in std_logic_vector(26 downto 0); -- dynamicaly determined maximum ctime value 
                   
      -- outputs
      hit_bits       : out std_logic_vector(4 downto 0);
      hit_win        : out std_logic_vector(8 downto 0);
      is_hit         : out std_logic := '0';                 -- there is a hit with valid timestamp 
      -- tbfifo_drdy    : out std_logic;                     -- data is ready
      self_trig      : out std_logic := '0';
      -- status ports
      sca_busy       : out std_logic := '0';                -- scalers counting is in progress
      -- scalers_arr    : out slv32(15 downto 0);           -- array(0 to 15) of slv32
      scalers_cnt    : out std_logic_vector(31 downto 0) := (others => '0');           -- array(0 to 15) of slv32
      -- fifo_cnt       : out std_logic_vector(15 downto 0); -- current fifo write address
      fifo_full_cnt  : out std_logic_vector(15 downto 0) := (others => '0')  -- fifo overflow counter

   );
end KLMTrigBitsProc;

architecture beh of KLMTrigBitsProc is 

    constant ctime_zero      : std_logic_vector(26 downto 0) := (others => '0');
    constant sca_max         : std_logic_vector(31 downto 0) := (others => '1');

-- ! Signals driven by synchronous processes:
    signal i_ctime           : std_logic_vector(26 downto 0) := (others => '0');
    signal i_ctime_trg       : std_logic_vector(26 downto 0) := (others => '0');
    signal i_ctime_max       : std_logic_vector(26 downto 0) := (others => '1'); -- dynamicaly determined maxinum ctime value
    signal i_localtrg        : std_logic := '0';
    signal i_localtrg_r      : std_logic := '0';
    signal i_lookback        : std_logic_vector(15 downto 0) := (others => '0');
    signal i_lookback_width  : std_logic_vector(15 downto 0) := (others => '0');
    signal i_lookback_max    : std_logic_vector(16 downto 0) := (others => '0');
    signal i_sca_clk_cnt_max     : std_logic_vector(7 downto 0) := (others => '0');
    signal i_sca_rst         : std_logic := '0';   -- reset scalers

    signal i_busy : std_logic_vector(CHECK_AND_READ_TIME_g - 1 downto 0);

    signal i_tbfifo_empty_r  : std_logic := '0';

    signal i_tbfifo_full_r   : std_logic := '0';
    signal i_fifo_full_cnt   : std_logic_vector(15 downto 0) := (others => '0');

    signal i_tb              : std_logic_vector(4 downto 0) := (others => '0');
    signal tb_r              : std_logic_vector(4 downto 0) := (others=>'0');
    signal tb_or_r           : std_logic_vector(TB_LATCH_DELAY_g downto 0) := (others=>'0');
    signal tb_r_ready      : std_logic := '0';

    signal i_cur_win         : slv9(TB_LATCH_DELAY_g + CUR_WIN_LATENCY_g downto 0) := (others=>(others => '0'));

    signal i_tbfifo_din      : std_logic_vector(40 downto 0) := (others => '0'); -- waddr(9)&trgbits(5)&ctime(27)
    signal i_tbfifo_wren     : std_logic := '0'; -- read enable for trigger bits FIFO

    signal clk_cnt           : std_logic_vector(23 downto 0):= (others => '1');
    signal sca_cnt_ena        : std_logic := '0';

    signal i_scalers_cnt     : std_logic_vector(31 downto 0):= (others => '0');

    type stale_hit_flushing_FSM is (IDLE, LET_FIFO_SETTLE);
    signal chk_stale_state : stale_hit_flushing_FSM := IDLE;
    signal i_tbfifo_rdstale  : std_logic := '0';

    signal ctime_diff_drain  : std_logic_vector(26 downto 0) := (others => '0');

    signal ctime_diff        : std_logic_vector(26 downto 0) := (others => '0');

    signal hit_not_too_old   : std_logic := '0'; -- timestamp is within lookback window

    type  proc_states is (IDLE, CHECK, READ );
    signal state             : proc_states := IDLE;
    -- signal rd_busy           : std_logic;  -- data is being read out from TB fifo
    signal i_tbfifo_rden     : std_logic := '0'; -- write enable for trigger bits FIFO
    signal i_hits_rd_cnt     : std_logic_vector(15 downto 0) := (others => '0'); -- not implemented. TODO

    signal i_is_hit          : std_logic := '0';


    signal tb_or             : std_logic := '0';
    signal tb_or_edge        : std_logic := '0';
    signal i_tbfifo_rden_res : std_logic := '0';


    signal i_tbfifo_dout     : std_logic_vector(40 downto 0) := (others => '0');
    signal i_tbfifo_full     : std_logic := '0';
    signal i_tbfifo_empty    : std_logic := '0';
    

begin


--------------------- ASYNCHRONOUS LOGIC ---------------------------------------------
    is_hit <= i_is_hit;
    tb_or       <= OR_REDUCE(i_tb);
    -- tb_or_edge  <= (not tb_or_2r) and tb_or_r;
    tb_or_edge  <= (not tb_or_r(TB_LATCH_DELAY_g))
                    and tb_or_r(TB_LATCH_DELAY_g - 1);
    fifo_full_cnt <= i_fifo_full_cnt;
    sca_busy <= sca_cnt_ena; 
    i_tbfifo_rden_res <= i_tbfifo_rdstale or i_tbfifo_rden;
    
    
    
    
--------------------- SYNCHRONOUS LOGIC ---------------------------------------------
    latch_inputs: process(clk)
    begin
        if rising_edge(clk) then
            i_ctime_trg <= ctime_trg;
            i_localtrg    <= localtrg;
            i_localtrg_r  <= i_localtrg;  -- delay localtrg for one clock cycle
            i_ctime     <= ctime;
            i_ctime_max <= ctime_max;
            -- latch configuration parameters
            i_lookback_width  <= lookback_width;
            i_lookback  <= lookback;
            i_lookback_max <= ('0' & i_lookback) + ('0' & i_lookback_width);
            i_sca_clk_cnt_max   <= sca_cnt_max;
            i_sca_rst <= rst or sca_rst;
        end if;
    end process;

    i_busy_proc: process(clk, localtrg)
    begin
        if rising_edge(clk) then
            if localtrg = '1' then
                i_busy <= "111111";
            else
                i_busy <= i_busy(i_busy'left - 1 downto 0) & '0';
            end if;
        end if;
    end process;

    ppln_fifo_empty: process(clk)
    begin
        if rising_edge(clk) then
            i_tbfifo_empty_r <= i_tbfifo_empty;
        end if;
    end process;


    ------------------------------------------------
    -- count fifo fulls
    ------------------------------------------------
    count_fifo_fulls: process(clk, rst)
    begin
        if rst = '1' then
            i_fifo_full_cnt <= (others => '0');
        elsif rising_edge(clk) then 
            i_tbfifo_full_r <= i_tbfifo_full;
            if i_tbfifo_full_r = '0' and i_tbfifo_full = '1' then
                i_fifo_full_cnt <= i_fifo_full_cnt + 1;
            end if;
        end if;
    end process;
    ------------------------------------------------


    ------------------------------------------------
    -- edge detect for trig bits
    ------------------------------------------------
    TB_EDGE_PROC : process(clk, asic_on, i_tb, tb_or, tb_or_edge)
    begin
        if rising_edge(clk) then
            if asic_on = '1' then
                i_tb  <= tb;
            else
                i_tb  <= (others => '0');
            end if;
            tb_r     <= i_tb ;
            tb_or_r <= tb_or_r(tb_or_r'left - 1 downto 0) & tb_or;
            tb_r_ready <= tb_or_edge;
        end if;
    end process TB_EDGE_PROC;
    ------------------------------------------------


    SYNC_WIN_WITH_TBs: process(clk, cur_win)
    begin
        if rising_edge(clk) then
            i_cur_win <= i_cur_win(i_cur_win'left - 1 downto 0) & cur_win;
        end if;
    end process;


    ------------------------------------------------
    -- TB timestamping with ctime
    ------------------------------------------------
    FILL_PROC : process(clk, tb_r, i_ctime, i_cur_win(i_cur_win'left), tb_r_ready)
    begin
        if rising_edge(clk) then
         
            if tb_r_ready = '1' then
                i_tbfifo_wren <= '1';
                self_trig <= '1';
                i_tbfifo_din  <= i_cur_win(i_cur_win'left) & tb_r & i_ctime;
            else
                self_trig <= '0';
                i_tbfifo_wren <= '0';
            end if;
        end if;
    end process FILL_PROC;
    ------------------------------------------------


    ------------------------------------------------
    -- Trigger bits scalers 
    ------------------------------------------------
    SCA_CNT_PERIOD : process(clk)
    begin
        if rising_edge(clk) then
            if i_sca_rst = '1' then
                sca_cnt_ena <= '0';
                clk_cnt <= (others => '0');
            else
                if clk_cnt(23 downto 16) < i_sca_clk_cnt_max then --count scalers for 65,536*(2^sca_cnt_max) clock cycles
                    clk_cnt <= clk_cnt + '1';
                    sca_cnt_ena <= '1';
                else
                    sca_cnt_ena <= '0';
                end if;
            end if;
        end if;
    end process;


        
    SCALERS_PROC : process(clk, i_sca_rst, sca_cnt_ena) --, tb_chan_2r)
    begin
        if rising_edge(clk) then
            if i_sca_rst = '1' then
                -- i_scalers_arr <= (others => (others => '0'));
                i_scalers_cnt <= (others => '0');
            else
                if sca_cnt_ena = '1' and tb_r_ready = '1' and tb_r(4) = '0' then -- 5th bit is omitted here
                    if i_scalers_cnt <= sca_max then 
                        i_scalers_cnt <= i_scalers_cnt + 1;
                    end if;
                    -- if i_scalers_arr(tb_chan_2r) <= sca_max then 
                    --    i_scalers_arr(tb_chan_2r) <= i_scalers_arr(tb_chan_2r) + 1;
                    -- end if;
                end if;
            end if;
        end if;
    end process SCALERS_PROC;


    ppln_scalers_out: process(clk)
    begin
        if rising_edge(clk) then
            -- scalers_arr <= i_scalers_arr;
            scalers_cnt <= i_scalers_cnt;
        end if;
    end process;
    ------------------------------------------------


    ------------------------------------------------
    -- track number of hits in the FIFO
    ------------------------------------------------
    -- process(clk, rst)
    -- begin
    --    if rst = '1' then
    --       i_fifo_cnt <= (others => '0');
    --    elsif rising_edge(clk) then
    --       if i_tbfifo_wren = '1' and i_tbfifo_rden_res = '0' then
    --          i_fifo_cnt <= i_fifo_cnt + 1;
    --       elsif i_tbfifo_wren = '0' and i_tbfifo_rden_res = '1' then
    --          i_fifo_cnt <= i_fifo_cnt - 1;
    --       end if;
    --    end if;
    -- end process;
    -- fifo_cnt <= i_fifo_cnt;
    ------------------------------------------------


    ------------------------------------------------
    -- flush stale data from the fifo
    ------------------------------------------------
    flush_stale_tbs: process(clk)
        variable count : integer range 0 to 3 := 0;
    begin
        if rising_edge(clk) then
            case chk_stale_state is

                when IDLE =>
                    count := 0;
                    if i_tbfifo_empty_r = '0' then
                        if ctime_diff_drain > ("0000000000" & i_lookback_max) then
                            i_tbfifo_rdstale <= not (i_busy(i_busy'left) or localtrg);
                            chk_stale_state <= LET_FIFO_SETTLE;
                        end if;
                    end if;

                when LET_FIFO_SETTLE => 
                    i_tbfifo_rdstale <= '0';
                    if count = 3 then
                        chk_stale_state <= IDLE;
                    else
                        count := count + 1;
                        chk_stale_state <= LET_FIFO_SETTLE;
                    end if;

             end case;
        end if;
     end process;


    -- calculate difference between current time and tb timestamp 
    calc_ctime_diff_drain: process(clk)
    begin
        if rising_edge(clk) then
            if i_ctime(26 downto 0) >= i_tbfifo_dout(26 downto 0) then
                ctime_diff_drain(26 downto 0) <= i_ctime(26 downto 0) - i_tbfifo_dout(26 downto 0);
            else
                ctime_diff_drain(26 downto 0) <= i_ctime_max - i_tbfifo_dout(26 downto 0) + i_ctime(26 downto 0); 
            end if;
        end if;
    end process;


    ------------------------------------------------
    -- calculate difference between trg time and tb timestamp 
    ------------------------------------------------
    calc_ctime_diff_trig: process(clk)
    begin
        if rising_edge(clk) then
            if i_ctime_trg >= i_tbfifo_dout(26 downto 0) then
                ctime_diff(26 downto 0) <= i_ctime_trg - i_tbfifo_dout(26 downto 0);
            else
                ctime_diff(26 downto 0) <= i_ctime_max - i_tbfifo_dout(26 downto 0) + i_ctime_trg; 
            end if;
        end if;
    end process;
    ------------------------------------------------


    ------------------------------------------------
    -- check if hit timestamp is within a lookback window
    ------------------------------------------------
    eval_ctime_diff_trig: process(clk)
    begin
        if rising_edge(clk) then
            if ctime_diff <= ("0000000000" & i_lookback_max) and ctime_diff >= ("00000000000" & i_lookback) then
                hit_not_too_old <= '1';
            else 
                hit_not_too_old <= '0';
            end if;
        end if;
    end process;
    ------------------------------------------------


    ------------------------------------------------
    -- read data fifo when triggered
    ------------------------------------------------
    proc_trig_FSM: process(clk, rst)
    begin
        if rst = '1' then
            state <= IDLE;
            -- tbfifo_drdy <= '0';
            i_tbfifo_rden <= '0';
            i_hits_rd_cnt <= (others => '0');
            -- i_trgbit_data <= (others => '0');
        elsif rising_edge(clk) then

            case state is
                when IDLE =>
                    -- tbfifo_drdy <= '0';
                    -- rd_busy <= '0';
                    i_tbfifo_rden   <= '0';
                    if i_localtrg_r = '1' then
                        state <= CHECK;
                        -- rd_busy <= '1';
                    else 
                        state <= IDLE;
                    end if;

                when CHECK =>
                    state  <= READ;
                
                when READ  =>
                    -- tbfifo_drdy <= '0';
                    if i_is_hit = '1' then
                        -- tbfifo_drdy <= '1';
                        hit_bits <= i_tbfifo_dout(31 downto 27);
                        hit_win <= i_tbfifo_dout(40 downto 32);
                        i_tbfifo_rden <= '1';
                        i_hits_rd_cnt <= i_hits_rd_cnt + 1;
                    else
                        hit_bits <= (others=>'0');
                        hit_win <= (others=>'0');
                        i_tbfifo_rden <= '0';
                    end if;
                    state <= IDLE;

                when OTHERS =>
                    state <= IDLE;

            end case;

       end if;
    end process;
 

    mark_valid_hits: process(clk)
    begin
        if rising_edge (clk) then
            i_is_hit <= '0';
            if i_tbfifo_empty = '0' and i_tbfifo_full = '0' then
                if hit_not_too_old = '1' then
                    i_is_hit <= '1';
                end if;
            end if;
        end if;
    end process;




--------------------- MODULE INSTANTIATIONS ---------------------------------------------

    ------------------------------------------------
    --- FIFO for trigger bits
    ------------------------------------------------
    tb_fifo_i : entity work.fifo_cc
    generic map(
        DATA_WIDTH => 41,
        DEPTH      => 7   
    )
    port map (
        clk    => clk,
        rst    => rst,
        din    => i_tbfifo_din,
        wen    => i_tbfifo_wren,
        ren    => i_tbfifo_rden_res,
        dout   => i_tbfifo_dout,
        full   => i_tbfifo_full,
        empty  => i_tbfifo_empty
    );


end beh;