beh Architecture Reference

Processes
latch_inputs	( clk )
i_busy_proc	( clk , localtrg )
ppln_fifo_empty	( clk )
count_fifo_fulls	( clk , rst )
TB_EDGE_PROC	( clk , asic_on , i_tb , tb_or , tb_or_edge )
SYNC_WIN_WITH_TBs	( clk , cur_win )
FILL_PROC	( clk , tb_r , i_ctime , i_cur_win (i_cur_win 'left) , tb_r_ready )
SCA_CNT_PERIOD	( clk )
SCALERS_PROC	( clk , i_sca_rst , sca_cnt_ena )
ppln_scalers_out	( clk )
flush_stale_tbs	( clk )
calc_ctime_diff_drain	( clk )
calc_ctime_diff_trig	( clk )
eval_ctime_diff_trig	( clk )
proc_trig_FSM	( clk , rst )
mark_valid_hits	( clk )

Constants
ctime_zero	std_logic_vector ( 26 downto 0 ) := ( others = > ' 0 ' )
sca_max	std_logic_vector ( 31 downto 0 ) := ( others = > ' 1 ' )

Types
stale_hit_flushing_FSM	( IDLE , LET_FIFO_SETTLE )
	flush_stale_tbs:
proc_states	( IDLE , CHECK , READ )
	proc_trig_FSM:

Signals
i_ctime	std_logic_vector ( 26 downto 0 ) := ( others = > ' 0 ' )
	latch_inputs:
i_ctime_trg	std_logic_vector ( 26 downto 0 ) := ( others = > ' 0 ' )
i_ctime_max	std_logic_vector ( 26 downto 0 ) := ( others = > ' 1 ' )
i_localtrg	std_logic := ' 0 '
i_localtrg_r	std_logic := ' 0 '
i_lookback	std_logic_vector ( 15 downto 0 ) := ( others = > ' 0 ' )
i_lookback_width	std_logic_vector ( 15 downto 0 ) := ( others = > ' 0 ' )
i_lookback_max	std_logic_vector ( 16 downto 0 ) := ( others = > ' 0 ' )
i_sca_clk_cnt_max	std_logic_vector ( 7 downto 0 ) := ( others = > ' 0 ' )
i_sca_rst	std_logic := ' 0 '
i_busy	std_logic_vector ( CHECK_AND_READ_TIME_g- 1 downto 0 )
	i_busy_proc:
i_tbfifo_empty_r	std_logic := ' 0 '
	ppln_fifo_empty:
i_tbfifo_full_r	std_logic := ' 0 '
	count_fifo_fulls:
i_fifo_full_cnt	std_logic_vector ( 15 downto 0 ) := ( others = > ' 0 ' )
i_tb	std_logic_vector ( 4 downto 0 ) := ( others = > ' 0 ' )
	TB_EDGE_PROC :
tb_r	std_logic_vector ( 4 downto 0 ) := ( others = > ' 0 ' )
tb_or_r	std_logic_vector ( TB_LATCH_DELAY_g downto 0 ) := ( others = > ' 0 ' )
tb_r_ready	std_logic := ' 0 '
i_cur_win	slv9 ( TB_LATCH_DELAY_g+ CUR_WIN_LATENCY_g downto 0 ) := ( others = > ( others = > ' 0 ' ) )
	SYNC_WIN_WITH_TBs:
i_tbfifo_din	std_logic_vector ( 40 downto 0 ) := ( others = > ' 0 ' )
	FILL_PROC :
i_tbfifo_wren	std_logic := ' 0 '
clk_cnt	std_logic_vector ( 23 downto 0 ) := ( others = > ' 1 ' )
	SCA_CNT_PERIOD :
sca_cnt_ena	std_logic := ' 0 '
i_scalers_cnt	std_logic_vector ( 31 downto 0 ) := ( others = > ' 0 ' )
	SCALERS_PROC :
chk_stale_state	stale_hit_flushing_FSM := IDLE
i_tbfifo_rdstale	std_logic := ' 0 '
ctime_diff_drain	std_logic_vector ( 26 downto 0 ) := ( others = > ' 0 ' )
	calc_ctime_diff_drain:
ctime_diff	std_logic_vector ( 26 downto 0 ) := ( others = > ' 0 ' )
	calc_ctime_diff_trig:
hit_not_too_old	std_logic := ' 0 '
	eval_ctime_diff_trig:
state	proc_states := IDLE
i_tbfifo_rden	std_logic := ' 0 '
i_hits_rd_cnt	std_logic_vector ( 15 downto 0 ) := ( others = > ' 0 ' )
i_is_hit	std_logic := ' 0 '
	mark_valid_hits:
tb_or	std_logic := ' 0 '
	Asynchronously driven signals.
tb_or_edge	std_logic := ' 0 '
i_tbfifo_rden_res	std_logic := ' 0 '
i_tbfifo_dout	std_logic_vector ( 40 downto 0 ) := ( others = > ' 0 ' )
i_tbfifo_full	std_logic := ' 0 '
i_tbfifo_empty	std_logic := ' 0 '

Instantiations
tb_fifo_i	fifo_cc <Entity fifo_cc>

Detailed Description

Definition at line 72 of file KLMTrigBitsProc.vhd.

Member Data Documentation

i_tbfifo_dout

i_tbfifo_dout std_logic_vector ( 40 downto 0 ) := ( others = > ' 0 ' )

Signal

Signals driven by instantiated entities: tb_fifo_i:

Definition at line 153 of file KLMTrigBitsProc.vhd.

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The documentation for this class was generated from the following file:

• klm_scint/source/KLMTrigBitsProc.vhd