WaveformReadout.vhd

library IEEE;
    use IEEE.STD_LOGIC_1164.ALL;
    use IEEE.NUMERIC_STD.ALL;
    use IEEE.STD_LOGIC_MISC.ALL;
    use IEEE.STD_LOGIC_UNSIGNED.ALL;
library unisim;
    use unisim.vcomponents.all;
library unimacro;
    use unimacro.vcomponents.all;
Library work;
    use work.klm_scint_pkg.all;
    -- use work.conc_intfc_pkg.all;
    -- use work.klm_scrod_pkg.all;
    -- use work.tdc_pkg.all;


-- #### Deficiencies:
--1. For now, we shift out whole windows only, if we calculate a finer ROI,
--then we can perhaps shift out fewer samples to save time.

entity WaveformReadout is
    generic (
        N_ASICS_g                 : integer := 10;
        FORCE_TRIG_BUF_DEPTH_g    : integer := 6;
        TRG_BUFF_DEPTH_g          : integer := 4;
        TRIG_QUEUE_DEPTH_g        : integer := 5;
        TQ_PROG_FULL_THRESH_g     : integer := 3;
        CALC_ROI_LAG_g            : integer := 2;
        T_WAIT_2C_IF_QUEUE_FULL_g : integer := 31;
        reset_buff_depth_g        : integer := 10;
        SLC_STAT_BUFF_DEPTH_g     : integer := 4;
        packet_type_g             : std_logic_vector(7 downto 0):= X"80"; -- marks scintillators hits for DataConcentrator
        N_readout_samples_g       : std_logic_vector(7 downto 0) := "10000000"; -- 128
        LAST_WINDOW_ADDRESS       : std_logic_vector(8 downto 0) := "111111111";
        N_BITS_AVG_g              : integer := 7;
        T_wait_busy_to_come_up_g  : integer := 31;
        FineLookback_win_g         : std_logic_vector(8 downto 0) := "000000001";
        max_proc_time_g           : std_logic_vector(15 downto 0) := "0011000110011100" -- 100us
    );
    port (
        -- main inputs
        clk                   : in  std_logic := '0';
        busy                  : out std_logic := '0';
        b2tt_runreset         : in  std_logic := '0';
        trig                  : in  trig_info_type_0 := null_trig_info_t0;

        -- signals with SamplingLgc
        ana_wr_ena_mask       : out TARGETX_analong_wr_ena_mask_t := null_TX_ana_wr_ena_mask;
        
        -- signals with HitDataSerializer
        localtrg              : in  std_logic := '0';
        force_trig            : in  std_logic := '0';
        sps_reset             : in  std_logic := '0';
        cur_win               : in  std_logic_vector(8 downto 0);
        
        -- nxt                   : in  std_logic := '0';
        -- tbfifo_rden           : out  std_logic_vector(9 downto 0) := (others=>'0');
        qt_fifo_rd_en         : in  std_logic := '0';
        qt_fifo_dout          : out std_logic_vector (17 downto 0) := (others=>'0');
        qt_fifo_empty         : out std_logic := '1';
        qt_fifo_err_cnt       : out std_logic_vector(15 downto 0); -- counter for daq data fifo overflows
        qt_fifo_evt_rdy       : out std_logic := '0';
        full_proc_cnt         : out std_logic_vector(15 downto 0) := (others=>'0');
        simp_proc_cnt         : out std_logic_vector(15 downto 0) := (others=>'0');
        null_proc_cnt         : out std_logic_vector(15 downto 0) := (others=>'0');

        -- pedestal RAM access
        RAM_IO                : inout std_logic_vector(7 downto 0) := (others => '0');
        RAM_WEb               : out std_logic := '1';
        RAM_OEb               : out std_logic := '0';
        RAM_ADDR              : out std_logic_vector(21 downto 0) := (others => '1');

        -- BusA signals
        BUSA_DO               : in  std_logic_vector(14 downto 0) := (others => '0');
        BUSA_RAMP             : out std_logic := '0';
        BUSA_CLR              : out std_logic := '0';
        BUSA_RD_COLSEL        : out std_logic_vector(5 downto 0) := (others => '0');
        BUSA_RD_ENA           : out std_logic := '0';
        BUSA_RD_ROWSEL        : out std_logic_vector(2 downto 0) := (others => '0');
        BUSA_SAMPLESEL        : out std_logic_vector(4 downto 0) := (others => '0');
        BUSA_SR_CLEAR         : out std_logic := '0';
        BUSA_SR_SEL           : out std_logic := '0';

        -- BusB signals
        BUSB_DO               : in  std_logic_vector(14 downto 0) := (others => '0');
        BUSB_RAMP             : out std_logic := '0';
        BUSB_CLR              : out std_logic := '0';
        BUSB_RD_COLSEL        : out std_logic_vector(5 downto 0) := (others => '0');
        BUSB_RD_ENA           : out std_logic := '0';
        BUSB_RD_ROWSEL        : out std_logic_vector(2 downto 0) := (others => '0');
        BUSB_SAMPLESEL        : out std_logic_vector(4 downto 0) := (others => '0');
        BUSB_SR_CLEAR         : out std_logic := '0';
        BUSB_SR_SEL           : out std_logic := '0';

        -- TargetX DC signals
        SAMPLESEL_ANY         : out std_logic_vector(9 downto 0) := (others => '0');
        SR_CLOCK              : out std_logic_vector(9 downto 0) := (others => '0');

        -- SCROD config registers
        wave_config           : in wave_config_t := default_wave_config;

        -- status registers
        wave_stat             : out waveform_stat_t := wave_stat_0;
        debug_wave_we         : out std_logic_vector(1 downto 0) := (others=>'0');
        debug_wave_din        : out slv12(1 downto 0) := (others=> (others=>'0'));
        SPS_hist_rd_data      : out slv16(1 downto 0) := (others=> (others=>'0'))
    );
end WaveformReadout;


architecture Behavioral of WaveformReadout is

    type trig_staging_FSM is (IDLE, WAIT_VALID, PROCESSING_REQ, WAIT_ACK);
    type modify_sampling_mask_FSM is (IDLE, WAIT_DONE);
    type ro_states is (IDLE, WAIT_RESET, CHECK_VALID, WAIT_WAVEFORM_READOUT, SEND_HITS, CHECK_DONE, STOP, SEND_SIMPLE);


--SYNCHRONOUS SIGNALS BY PROCESS WHICH DRIVES THEM
 
    signal wave_stat_i : wave_stat_vec(SLC_STAT_BUFF_DEPTH_g - 1 downto 0) := (others => wave_stat_0);

    signal wave_config_q1 : wave_config_t := default_wave_config;
    signal wave_config_q2 : wave_config_t := default_wave_config;
    signal wave_config_q3 : wave_config_t := default_wave_config;
    signal wave_config_q4 : wave_config_t := default_wave_config;
    signal wave_config_q5 : wave_config_t := default_wave_config;
    signal wave_config_q6 : wave_config_t := default_wave_config;

    signal i_b2tt_runreset : std_logic_vector(reset_buff_depth_g - 1 downto 0);
    signal busA_reset      : std_logic := '0';
    signal busB_reset      : std_logic := '0';

    signal or_busy_sr           : std_logic_vector(5 downto 0) := (others => '0');
    signal either_bus_busy     : std_logic := '0';

    signal i_localtrg : std_logic_vector(TRG_BUFF_DEPTH_g - 1 downto 0);

    signal force_trig_sr : std_logic_vector(FORCE_TRIG_BUF_DEPTH_g-1 downto 0) := (others => '0');
    signal sps_reset_sr  : std_logic_vector(FORCE_TRIG_BUF_DEPTH_g-1 downto 0) := (others => '0');

    signal meas_peds_ena       : std_logic;
    signal i_N_readout_samples : std_logic_vector(7 downto 0) := "00100000";
    signal i_RAM_WEb           : std_logic := '1';
    signal i_RAM_din           : std_logic_vector(7 downto 0) := (others => '0');
    signal RAM_din             : std_logic_vector(7 downto 0) := (others => '0');
    signal RAM_rw              : std_logic := '1';

    signal single_bus_ena    : std_logic := '0';
    signal SPS_measure_start : std_logic_vector(1 downto 0) := "00";

    signal i_trig_bits       : slv5(9 downto 0) := (others=>(others=>'0'));
    signal starting_win_samp : slv14(9 downto 0) := (others => (others=>'0'));
    signal first_dig_win     : std_logic_vector(8 downto 0) := (others=>'0');
    signal last_dig_win      : std_logic_vector(8 downto 0) := (others=>'0');
    signal asic_mask         : std_logic_vector(9 downto 0) := (others => '0');

    signal trig_staging      : trig_staging_FSM := IDLE;
    signal trig_in_t0        : trig_info_type_0 := null_trig_info_t0;
    signal calc_roi_ena      : std_logic := '0';
    signal trg_proc_busy     : std_logic := '0';
    signal mask_windows      : std_logic := '0';
    signal trig_queue_wr_ena : std_logic := '0';

    signal wr_ptr             : integer range 0 to TRIG_QUEUE_DEPTH_g - 1 := 0;
    signal rd_ptr             : integer range 0 to TRIG_QUEUE_DEPTH_g - 1 := 0;
    signal wr_ptr_nxt         : integer range 0 to TRIG_QUEUE_DEPTH_g - 1 := 0;
    signal rd_ptr_nxt         : integer range 0 to TRIG_QUEUE_DEPTH_g - 1 := 0;
    signal queue_empty        : std_logic := '1';
    signal queue_above_thresh : std_logic := '0';
    signal queue_full         : std_logic := '0';
    signal start_readout      : std_logic := '0';
    signal trig_queue         : trig_queue_type(TRIG_QUEUE_DEPTH_g - 1 downto 0) := (others => null_trig_info_t1); -- triggers on deck
    signal trig_q0            : trig_info_type_1 := null_trig_info_t1;                               

    signal modify_sampling_mask  : modify_sampling_mask_FSM := IDLE;
    signal mask_ack              : std_logic := '0';
    signal unmask_ack            : std_logic := '0';
    signal i_ana_wr_ena_mask       : TARGETX_analong_wr_ena_mask_t := null_TX_ana_wr_ena_mask;
    
    signal ro_state          : ro_states := IDLE;
    signal hit_bldr_fsm_busy : std_logic := '0';
    signal ro_reset          : std_logic := '0';
    signal daq_axis_i        : std_logic := '0';
    signal daq_chan_i        : std_logic_vector(6 downto 0) := (others => '0');
    signal daq_chan_base     : std_logic_vector(6 downto 0) := (others => '0');
    signal tb5               : std_logic := '0';
    signal simp              : std_logic := '0';
    signal le_time_i         : std_logic_vector(13 downto 0) := (others => '0');
    signal peak_i            : std_logic_vector(11 downto 0) := (others => '0');
    signal daq_start_ro      : std_logic := '0';
    signal i_full_proc_cnt   : std_logic_vector(15 downto 0) := (others => '0');
    signal i_simp_proc_cnt   : std_logic_vector(15 downto 0) := (others => '0');
    signal i_null_proc_cnt   : std_logic_vector(15 downto 0) := (others => '0');
    signal daq_asic_mask     : std_logic_vector(9 downto 0) := (others => '0');
    signal simp_asic_mask    : std_logic_vector(9 downto 0) := (others => '0');
    signal unmask_windows    : std_logic := '0';
    signal rx_features_ack   : std_logic_vector(1 downto 0) := (others => '0');
    signal ser_run_i  : std_logic := '0';
    signal HitData_i  : KlmScrodHitDataType := KlmScrodHitDataNull;

    signal ser_run  : std_logic := '0';
    signal HitData  : KlmScrodHitDataType := KlmScrodHitDataNull;

 

    signal or_dig_busy       : std_logic := '0';
    signal single_bus_reset  : std_logic := '0';
    signal disambig_tb5      : std_logic := '1';
    signal or_busy_status    : std_logic := '0';

-- SIGNALS DRIVEN BY INSTANTIATED ENTITIES

    signal trig_in_t1    : trig_info_type_1 := null_trig_info_t1; -- copy of input trig with ROI added

    signal i_ped_fetch_asic_no : slv3(1 downto 0);-- := (others => "000");
    signal ped_fetch_chan      : slv4(1 downto 0) := (others => "0000");
    signal ped_win_samp_start  : slv14(1 downto 0) := (others=>(others=>'0'));
    signal ped_fetch_ena       : std_logic_vector(1 downto 0) := (others => '0');
    signal BUSA_WINSEL         : std_logic_vector(8 downto 0) := (others => '0');
    signal BUSB_WINSEL         : std_logic_vector(8 downto 0) := (others => '0');
    signal rx_features_ena     : std_logic_vector(1 downto 0) := (others => '0');
    signal last_hit            : std_logic_vector(1 downto 0) := "00";
    signal peak              : slv12(1 downto 0) := (others => "000000000000");
    signal le_time             : slv14(1 downto 0) := (others => "00000000000000");
    signal daq_chan            : slv7(1 downto 0) := (others => "0000000");
    signal DigStoreProcBusy    : std_logic_vector(1 downto 0) := "00";
    signal DigNShiftBusy       : std_logic_vector(1 downto 0) := "00";
    signal DigBusy             : std_logic_vector(1 downto 0) := "00";
    signal ShiftOutWinBusy     : std_logic_vector(1 downto 0) := "00";
    signal ShiftOutSampBusy    : std_logic_vector(1 downto 0) := "00";
    signal FeatExtBusy         : std_logic_vector(1 downto 0) := "00";
    signal PedFetchQueueBusy   : std_logic_vector(1 downto 0) := "00";
    signal avg_peds_busy       : std_logic_vector(1 downto 0) := "00";
    signal wr_peds2sram_ena    : std_logic_vector(1 downto 0) := (others=>'0');
    signal even_sample         : slv12(1 downto 0) := (others => (others=>'0'));
    signal odd_sample          : slv12(1 downto 0) := (others => (others=>'0'));
    signal sram_asic_addr      : slv3(1 downto 0) := (others=>(others=>'0'));
    signal sram_chan_addr      : slv4(1 downto 0) := (others=>(others=>'0'));
    signal sram_samp_addr      : slv4(1 downto 0) := (others=>(others=>'0'));

    signal ped_fetch_ack       : std_logic_vector(1 downto 0) := (others => '0');
    signal ped_fifo_asic_sel   : std_logic_vector(4 downto 0) := (others => '0');
    signal ped_fifo_chan_sel   : std_logic_vector(3 downto 0) := (others => '0');
    signal ped_fifo_wr_ena     : std_logic_vector(1 downto 0) := (others => '0');
    signal ped_fifo_din        : std_logic_vector(11 downto 0) := (others => '0');
    signal RAM_rd_addr         : std_logic_vector(21 downto 0) := (others => '0');

    signal RAM_wr_addr      : std_logic_vector(21 downto 0) := (others => '0');
    signal wr_peds2sram_ack : std_logic_vector(1 downto 0) := (others=>'0');

    signal ped_meas_win         : std_logic_vector(8 downto 0) := (others=>'0');
    signal ped_start_ro         : std_logic := '0';
    signal prime_fifos          : std_logic := '0';
    signal avg_peds_ena         : std_logic := '0';
    signal summing_ena          : std_logic := '0';

    -- HitData_Serializer_i :
    signal ser_busy     : std_logic := '0';
    
    signal RAM_do :  std_logic_vector(7 downto 0) := (others => '0');

begin

------------------- ASYNCHRONOUS LOGIC ---------------------------------------------

    single_bus_reset <= ro_reset; -- or rst_from_sps_fsm;
    BUSA_RD_ROWSEL <= BUSA_WINSEL(2 downto 0); -- Kurtis says bit pattern is more complicated...
    BUSB_RD_ROWSEL <= BUSB_WINSEL(2 downto 0); -- ...may be shuffled in UCF or elsewhere in firmware
    BUSA_RD_COLSEL <= BUSA_WINSEL(8 downto 3);
    BUSB_RD_COLSEL <= BUSB_WINSEL(8 downto 3);
    -- dbg_start_ro <= (force_trig_sr(force_trig_sr'left) and not (wave_config_q6.measure_peds or wave_config_q6.use_loop_trig));
    -- asic_chan_win_sel <= wave_config_q6.measure_peds & wave_config_q6.use_ftsw_trig;
    -- bus_mask <= daq_bus_mask or ped_bus_mask;
    ana_wr_ena_mask <= i_ana_wr_ena_mask;
    trig_in_t1.wr_time <= trig_in_t0.wr_time;
    trig_in_t1.mask <= trig_in_t0.mask;
    trig_in_t1.ctime <= trig_in_t0.ctime;
    trig_in_t1.bits <= trig_in_t0.bits;
    or_dig_busy <= DigBusy(0) or DigBusy(1);
    or_busy_status <= or_reduce(DigStoreProcBusy)
                      or or_reduce(DigNShiftBusy)
                      or or_reduce(DigBusy)
                      or or_reduce(ShiftOutWinBusy)
                      or or_reduce(ShiftOutSampBusy)
                      or or_reduce(FeatExtBusy)
                      or or_reduce(PedFetchQueueBusy);
    -- trg_proc_cnt <= i_trg_proc_cnt(31 downto 24) & i_trg_proc_cnt(7 downto 0); 
    full_proc_cnt <= i_full_proc_cnt;
    simp_proc_cnt <= i_simp_proc_cnt;
    null_proc_cnt <= i_null_proc_cnt;
    -- or_calc_roi_busy <= or_reduce(calc_roi_busy);
    disambig_tb5 <= wave_config_q6.use_ftsw_trig;

--------------------- SYNCHRONOUS LOGIC ---------------------------------------------

    ppln_stat: process(clk, wave_stat_i)
    begin
        wave_stat <= wave_stat_i(wave_stat_i'left);
        wave_stat_i(wave_stat_i'left downto 1) <= wave_stat_i(wave_stat_i'left - 1 downto 0);
    end process;
    
    conf_dffs: process(clk, wave_config, wave_config_q1, wave_config_q2,
                       wave_config_q3, wave_config_q4, wave_config_q5)
    begin
        if rising_edge(clk) then
            wave_config_q1 <= wave_config;
            wave_config_q2 <= wave_config_q1;
            wave_config_q3 <= wave_config_q2;
            wave_config_q4 <= wave_config_q3;
            wave_config_q5 <= wave_config_q4;
            wave_config_q6 <= wave_config_q5;
        end if;
    end process conf_dffs;

    rst_buff: process(clk, b2tt_runreset, i_b2tt_runreset)
    begin
        if rising_edge(clk) then
            i_b2tt_runreset(reset_buff_depth_g - 1 downto 1) <= i_b2tt_runreset(reset_buff_depth_g - 2 downto 0);
            i_b2tt_runreset(0) <= b2tt_runreset;
            busA_reset <= single_bus_reset;
            busB_reset <= single_bus_reset;
        end if;
    end process rst_buff;


    busy_lgc: process(clk, or_busy_status, queue_full)
    begin
        if rising_edge(clk) then
            or_busy_sr <= or_busy_sr(or_busy_sr'left - 1 downto 0) & or_busy_status;
            either_bus_busy <= or_busy_sr(or_busy_sr'left) or or_busy_sr(0);
            wave_stat_i(0).wave_proc_busy <= hit_bldr_fsm_busy;
            -- busy <= localtrg or calc_roi_busy(0) or calc_roi_busy(1) or queue_full;
            busy <= trg_proc_busy or queue_full;
        end if;
    end process busy_lgc;
    
    
    trg_buff: process(clk, localtrg)
    begin
        if rising_edge(clk) then
            i_localtrg <= i_localtrg(i_localtrg'left - 1 downto 0) & localtrg;
        end if;
    end process;
    

    force_trig_buffer: process(clk, force_trig)
    begin
        if rising_edge(clk) then
            force_trig_sr <= force_trig_sr(force_trig_sr'left - 1 downto 0) & force_trig;
        end if;
    end process;
    
    
    sps_reset_buffer: process(clk, sps_reset)
    begin
        if rising_edge(clk) then
            sps_reset_sr <= sps_reset_sr(sps_reset_sr'left - 1 downto 0) & sps_reset;
        end if;
    end process;
    
    
    ----------------------------------------------------------------------------
    -- ADDRESS MULTIPLEXER AND PIPELINE FOR SRAM CONTROL --
    ----------------------------------------------------------------------------
    SRAM_mux: process (clk, wave_config_q6.measure_peds, force_trig_sr, i_RAM_din,
            RAM_wr_addr, RAM_rd_addr, i_RAM_WEb)
    begin
        if rising_edge(clk) then
            RAM_din  <= i_RAM_din; -- DFF for matching phase with address
            RAM_WEb <= i_RAM_WEb; -- DFF for matching phase with address
            if wave_config_q6.measure_peds = '1' then
                RAM_rw <= '0';
                RAM_OEb <= '1';
                RAM_ADDR <= RAM_wr_addr;
                meas_peds_ena <= force_trig_sr(force_trig_sr'left);
                i_N_readout_samples <= "00100000";
            else
                RAM_rw <= '1';
                RAM_OEb <= '0';
                RAM_ADDR <= RAM_rd_addr;
                meas_peds_ena <= '0';
                i_N_readout_samples <= N_readout_samples_g;
            end if;
        end if;
    end process SRAM_mux;


    ena_logic: process(clk, ped_start_ro, daq_start_ro)
    begin
        if rising_edge(clk) then
            single_bus_ena <= ped_start_ro or daq_start_ro;
        end if;
    end process ena_logic;


    asic_chan_win_mux: process(clk, wave_config_q6.measure_peds, ped_meas_win, daq_asic_mask, trig_q0)
    begin
        if rising_edge(clk) then
            if wave_config_q6.measure_peds = '1' then
                i_trig_bits <= (others=>(others=>'1'));
                asic_mask <= (others=>'1');
                starting_win_samp <= (others=> ped_meas_win & "00000");
                first_dig_win <= ped_meas_win;
                last_dig_win  <= ped_meas_win;
            else
                first_dig_win <= trig_q0.first_dig_win - FineLookback_win_g;
                last_dig_win  <= trig_q0.last_dig_win - FineLookback_win_g + (N_readout_samples_g(7 downto 5) - "001");
                asic_mask <= daq_asic_mask;
                for i in 0 to 9 loop
                    starting_win_samp(i) <= (trig_q0.wr_time(i) & "00000") - (FineLookback_win_g & "00000");
                    i_trig_bits(i) <= trig_q0.bits(i); -- used by SingleBusProcessing to make a channel mask
                end loop;
            end if;
        end if;
    end process asic_chan_win_mux;
    ----------------------------------------------------------------------------



    ------------------------------------------------
    --- Process Triggers: Calc ROI, fill queue, mask windows  --  initiated by in port 'localtrg'
    ------------------------------------------------
    trg_proc: process(clk, i_localtrg(i_localtrg'left), queue_full, mask_ack, trig)
        variable count : integer range 0 to (CALC_ROI_LAG_g + N_ASICS_g);
    begin
        if rising_edge(clk) then
             case trig_staging is
                
                when IDLE =>
                    count := 0;
                    if i_localtrg(i_localtrg'left) = '1' and queue_full = '0' then
                        trg_proc_busy <= '1';
                        trig_staging <= WAIT_VALID;
                    else
                        trg_proc_busy <= '0';
                        trig_staging <= IDLE;
                    end if;
                
                when WAIT_VALID =>
                    -- tbfifo_rden <= "0000000000";
                    -- if trig.ready = "1111111111" then
                        trig_in_t0 <= trig; -- tb_fifo is 1st-wd fall-through, so trig ready before tbfifo_rden
                        -- tbfifo_rden <= trig.mask;
                        -- tbfifo_rden <= "1111111111"; -- mask taken care of in KLMTrigBitsProc
                        calc_roi_ena <= '1';
                        trig_staging <= PROCESSING_REQ;
                    -- else
                        -- trig_staging <= WAIT_VALID;
                    -- end if;
                
                when PROCESSING_REQ =>
                    -- tbfifo_rden <= "0000000000";
                    calc_roi_ena <= '0';
                    if count < (CALC_ROI_LAG_g + N_ASICS_g) then
                        count := count + 1;
                    -- if calc_roi_ena = '1' or calc_roi_busy(1) = '1' or calc_roi_busy(0) = '1' then -- wait for calcROI
                        trig_staging <= PROCESSING_REQ;
                    -- elsif or_calc_roi_busy = '1' then
                    --     trig_staging <= PROCESSING_REQ;
                    else
                        mask_windows <= '1'; -- stop TargetX sampling over ROI
                        trig_queue_wr_ena <= '1'; -- trig_in_t1 ready w/ROI info added. Add to queue.
                        trig_staging <= WAIT_ACK;
                    end if;
                    
                when WAIT_ACK =>
                    trig_queue_wr_ena <= '0';
                    if mask_ack = '1' then -- wait for verification that masking was done
                        mask_windows <= '0';
                        trig_staging <= IDLE;
                    else
                        trig_staging <= WAIT_ACK;
                    end if;

            end case;
        end if;
    end process trg_proc;


    ------------------------------------------------
    --- Queue triggers and initiate readout
    ------------------------------------------------
    trg_queue: process(clk, i_b2tt_runreset, trig_queue_wr_ena, queue_full, queue_empty, hit_bldr_fsm_busy, trig_in_t1)
        -- variable wr_ptr     : integer range 0 to TRIG_QUEUE_DEPTH_g - 1 := 0;
        -- variable rd_ptr     : integer range 0 to TRIG_QUEUE_DEPTH_g - 1 := 0;
        -- variable wr_ptr_nxt : integer range 0 to TRIG_QUEUE_DEPTH_g - 1 := 0;
        variable above_thresh_but_not_full : std_logic := '0';
    begin
        if rising_edge(clk) then
            queue_above_thresh <= above_thresh_but_not_full or queue_full;
            if i_b2tt_runreset(i_b2tt_runreset'left) = '1' then
                queue_empty <= '1';
                queue_full <= '0';
                start_readout <= '0';
                rd_ptr <= wr_ptr;
            else
                if wr_ptr = (TRIG_QUEUE_DEPTH_g - 1) then
                    wr_ptr_nxt <= 0;
                else
                    wr_ptr_nxt <= wr_ptr + 1;
                end if;
                if wr_ptr >= rd_ptr then
                    if (wr_ptr - rd_ptr) >= TQ_PROG_FULL_THRESH_g then
                        above_thresh_but_not_full := '1';
                    else
                        above_thresh_but_not_full := '0';
                    end if;
                else
                    if (TRIG_QUEUE_DEPTH_g - (rd_ptr - wr_ptr)) >= TQ_PROG_FULL_THRESH_g then
                        above_thresh_but_not_full := '1';
                    else
                        above_thresh_but_not_full := '0';
                    end if;
                end if;
                if rd_ptr = (TRIG_QUEUE_DEPTH_g - 1) then
                    rd_ptr_nxt <= 0;
                else
                    rd_ptr_nxt <= rd_ptr + 1;
                end if;
                if trig_queue_wr_ena = '1' and queue_full = '0'then
                    trig_queue(wr_ptr) <= trig_in_t1; -- Add trigger to queue
                    if wr_ptr = (TRIG_QUEUE_DEPTH_g - 1) then -- increment write pointer
                        wr_ptr <= 0;
                    else
                        wr_ptr <= wr_ptr + 1;
                    end if;
                    if wr_ptr_nxt = rd_ptr then
                        queue_full <= '1';
                    end if;
                    queue_empty <= '0';
                elsif queue_empty = '0' and hit_bldr_fsm_busy = '0' and start_readout = '0' then
                    start_readout <= '1'; -- initiate readout
                    trig_q0 <= trig_queue(rd_ptr); -- trig_q0 is the one being processed
                    if rd_ptr = (TRIG_QUEUE_DEPTH_g - 1) then -- increment read pointer
                        rd_ptr <= 0;
                    else
                        rd_ptr <= rd_ptr + 1;
                    end if;
                    if rd_ptr_nxt = wr_ptr then
                        queue_empty <= '1';
                    end if; 
                    queue_full <= '0';
                else
                    start_readout <= '0';
                end if;
            end if;
        end if;
    end process trg_queue;


    ------------------------------------------------
    --- Mask / Unmask windows for waveform sampling
    ------------------------------------------------
    mask_unmask_proc: process(clk, mask_windows, unmask_windows,
                              trig_in_t1.first_dig_win, trig_q0.first_dig_win)
        variable count : integer range 0 to 3;
    begin
        if rising_edge(clk) then
            case modify_sampling_mask is
            
                when IDLE =>
                    count := 0;
                    i_ana_wr_ena_mask <= null_TX_ana_wr_ena_mask;
                    mask_ack <= '0';
                    unmask_ack <= '0';
                    if mask_windows = '1' then -- mask off windows when trigger goes into queue
                        mask_ack <= '1'; -- acknowledge signal to arbitrate collisions
                        i_ana_wr_ena_mask.ena <= '1';
                        i_ana_wr_ena_mask.mask_bit <= '0';
                        i_ana_wr_ena_mask.win_start <= trig_in_t1.first_dig_win;
                        i_ana_wr_ena_mask.n_win <= "0010" + i_N_readout_samples(7 downto 5); --FIXME: use last dig_win
                        modify_sampling_mask <= WAIT_DONE;
                    elsif unmask_windows = '1' then -- unmask windows when current trigger is done processing
                        unmask_ack <= '1';
                        i_ana_wr_ena_mask.ena <= '1';
                        i_ana_wr_ena_mask.mask_bit <= '1';
                        i_ana_wr_ena_mask.win_start <= trig_q0.first_dig_win;
                        i_ana_wr_ena_mask.n_win <= "0010" + i_N_readout_samples(7 downto 5); --FIXME: use last dig_win
                        modify_sampling_mask <= WAIT_DONE;
                    else
                        modify_sampling_mask <= IDLE;
                    end if;
                    
                when WAIT_DONE =>
                    mask_ack <= '0';
                    unmask_ack <= '0';
                    -- if count = (N_readout_samples_g(7 downto 5) + "010") then
                    if count = 3 then
                        i_ana_wr_ena_mask <= null_TX_ana_wr_ena_mask;
                        modify_sampling_mask <= IDLE;
                    else
                        count := count + 1;
                        modify_sampling_mask <= WAIT_DONE;
                    end if;
            
            end case;
        end if;
    end process;

   -----------------------------------------------------------------------------
   --- KLM Hit Builder -- initiated when HitQueue not empty and this FSM not busy
   -----------------------------------------------------------------------------
    hit_bldr: process(clk, i_b2tt_runreset, start_readout, trig_q0,
            rx_features_ena, peak, le_time, daq_chan, i_full_proc_cnt, i_simp_proc_cnt, i_null_proc_cnt,
            last_hit, unmask_ack, wave_config_q6.use_ftsw_trig,
            queue_above_thresh)
        variable count : integer range 0 to T_WAIT_2C_IF_QUEUE_FULL_g := 0;
        variable i_last_hit : std_logic_vector(1 downto 0) := "00";
        variable i_first_hit : std_logic := '1';
        variable i_queue_getting_full : std_logic := '0';
    begin
        if rising_edge(clk) then
            if i_b2tt_runreset(i_b2tt_runreset'left) = '1' then
                ro_state <= IDLE;
                ser_run_i <= '0';
                qt_fifo_evt_rdy <= '0';
                ro_reset <= '1';
                i_full_proc_cnt <= (others=>'0');
                i_simp_proc_cnt <= (others=>'0');
                i_null_proc_cnt <= (others=>'0');
            else

                case ro_state is

                    WHEN IDLE =>
                        TB5 <= '0';
                        ro_reset <= '0';
                        ser_run_i <= '0';
                        qt_fifo_evt_rdy <= '0';
                        HitData_i.last_hit <= '0';
                        i_first_hit := '1';
                        -- HitData_i.null_hit <= '1';
                        daq_chan_base <= (others=>'0');
                        daq_chan_i <= (others=>'0');
                        le_time_i <= (others=>'0');
                        peak_i <= (others=>'0');
                        if start_readout = '1' then -- initiated by trig_queue whenever queue is nonempty and readout is not busy
                            
                            count := 0;
                            ro_reset <= '1';
                            hit_bldr_fsm_busy <= '1';
                            ro_state <= WAIT_RESET;
                        else
                            hit_bldr_fsm_busy <= '0';
                            ro_state <= IDLE;
                        end if;

                      -- FIXME: CHECK IF STATE CAN BE REMOVED
                      When WAIT_RESET => -- soft reset to make sure staging fifos are empty before processing new trigger
                        if count < 3 then
                            ro_reset <= '1';
                        else
                            ro_reset <= '0';
                        end if;
                        if count < T_WAIT_2C_IF_QUEUE_FULL_g then
                            count := count + 1;
                            ro_state <= WAIT_RESET;
                        else
                            count := 0;
                            ro_state <= CHECK_VALID;
                        end if;


                    -- wait until event data is valid
                    WHEN CHECK_VALID =>
                        i_last_hit(0) := not or_reduce(trig_q0.mask(4 downto 0));
                        i_last_hit(1) := not or_reduce(trig_q0.mask(9 downto 5));
                        daq_asic_mask <= trig_q0.mask;
                        simp_asic_mask <= trig_q0.mask;
                        if or_reduce(trig_q0.mask) = '1' then
                            HitData_i.null_hit <= '0';
                            if queue_above_thresh = '0' then
                                i_queue_getting_full := '0';
                                daq_start_ro <= '1';
                                simp <= '0';
                                i_full_proc_cnt <= i_full_proc_cnt + '1';
                                ro_state <= WAIT_WAVEFORM_READOUT;
                            else
                                i_queue_getting_full := '1';
                                simp <= '1';
                                i_simp_proc_cnt <= i_simp_proc_cnt + '1';
                                ro_state <= SEND_SIMPLE;
                            end if;
                        else
                            HitData_i.null_hit <= '1';
                            i_null_proc_cnt <= i_null_proc_cnt + '1';
                            ro_state <= SEND_HITS;
                        end if;


                    WHEN WAIT_WAVEFORM_READOUT =>
                        daq_start_ro <= '0';
                        if rx_features_ena(0) = '1' then
                            rx_features_ack <= "01";
                            daq_axis_i <= '0';
                            -- HitData_i.null_hit <= null_hit(0);
                            peak_i <= peak(0);
                            le_time_i <= le_time(0);
                            daq_chan_i <= daq_chan(0);
                            i_last_hit(0) := last_hit(0); -- BusA last hit
                            -- HitData_i.last_hit <= last_hit(0) and i_last_hit(1);
                            ro_state <= SEND_HITS;
                        elsif rx_features_ena(1) = '1' then
                            rx_features_ack <= "10";
                            daq_axis_i <= '1';
                            -- HitData_i.null_hit <= null_hit(1);
                            peak_i <= peak(1);
                            le_time_i <= le_time(1);
                            daq_chan_i <= daq_chan(1);
                            i_last_hit(1) := last_hit(1); -- BusB last hit
                            -- HitData_i.last_hit <= last_hit(1) and i_last_hit(0);
                            ro_state <= SEND_HITS;
                        else
                            ro_state <= WAIT_WAVEFORM_READOUT;
                        end if;


                    WHEN SEND_HITS =>
                        if i_queue_getting_full = '1' then
                            i_last_hit(0) := not or_reduce(simp_asic_mask(4 downto 0));
                            i_last_hit(1) := not or_reduce(simp_asic_mask(9 downto 5));
                        end if;
                        rx_features_ack <= "00";
                        if ser_busy = '1' then
                            ro_state <= SEND_HITS;
                        else
                            HitData_i.first_hit <= i_first_hit;
                            HitData_i.last_hit <= i_last_hit(1) and i_last_hit(0);
                            ser_run_i <= wave_config_q6.use_ftsw_trig; -- initiate transaction
                            ro_state <= CHECK_DONE;
                        end if;


                    WHEN CHECK_DONE  =>
                        ser_run_i <= '0';
                        i_first_hit := '0';
                        if i_last_hit(1) = '1' and i_last_hit(0) = '1' THEN
                            qt_fifo_evt_rdy <= wave_config_q6.use_ftsw_trig;
                            unmask_windows <= '1';
                            -- i_trg_proc_cnt <= i_trg_proc_cnt + '1';
                            ro_state <= STOP;
                        else
                            if i_queue_getting_full = '1' then
                                ro_state <= SEND_SIMPLE;
                            else
                                ro_state <= WAIT_WAVEFORM_READOUT;
                            end if;
                        end if;


                    WHEN STOP =>
                        ser_run_i <= '0';
                        if unmask_ack = '1' then -- VERY IMPORTANT: stay here until sampling mask is removed.
                            unmask_windows <= '0';
                            ro_state <= IDLE;
                        else
                            ro_state <= STOP;
                        end if;

                    When SEND_SIMPLE =>
                        TB5 <= trig_q0.bits(count)(4);
                        daq_chan_i <= daq_chan_base + ("000" & trig_q0.bits(count)(3 downto 0) - '1');
                        if count < 5 then
                            daq_axis_i <= '0';
                        else
                            daq_axis_i <= '1';
                        end if;
                        if simp_asic_mask(count) = '1' or count = 9 then
                            simp_asic_mask(count) <= '0';
                            ro_state <= SEND_HITS;
                        else
                            ro_state <= SEND_SIMPLE;
                        end if;
                        if count = 4 then
                            daq_chan_base <= "0000000";
                        else
                            daq_chan_base <= daq_chan_base + "0001111";
                        end if;
                        count := count + 1;

                end case;
            end if;
        end if;

    end process hit_bldr;


    ppln_hit_data: process(clk, daq_axis_i, daq_chan_i, trig_q0.ctime, simp, TB5,
                           le_time_i, peak_i, HitData_i, ser_run_i)
    begin
        if rising_edge(clk) then
            HitData_i.word1 <= packet_type_g & daq_axis_i & daq_chan_i;
            HitData_i.word2 <= trig_q0.ctime;
            HitData_i.word3 <= simp & TB5 & le_time_i;
            HitData_i.word4 <= "0000" & peak_i;
            HitData <= HitData_i;
            ser_run <= ser_run_i;
        end if;
    end process;




---------------------BEGIN MODULES ---------------------------------------------
    CALC_ROI: entity work.CalculateROI
    generic map (
        ARR_DEPTH_g => N_ASICS_g,
        VEC_WIDTH_g => 9
    )
    port map (
        clk         => clk,
        ena         => calc_roi_ena,
        -- busy        => calc_roi_busy(i),
        vec_arr     => trig_in_t0.wr_time,
        arr_mask    => trig_in_t0.mask,
        first_vec   => trig_in_t1.first_dig_win,
        last_vec    => trig_in_t1.last_dig_win
    );


    busA : entity work.SingleBusProcessing
    generic map (
        N_BITS_AVG_g => N_BITS_AVG_g
    )
    port map (
        -- main inputs
        clk                => clk,
        rst                => busA_reset,
        ped_sub_ena        => wave_config_q6.ped_sub_ena,
        disambig_tb5       => disambig_tb5,
        measure_peds       => wave_config_q6.measure_peds,
        stream_peds        => wave_config_q6.stream_peds,
        ena                => single_bus_ena,
        win_samp_start     => starting_win_samp(4 downto 0),
        trig_bits          => i_trig_bits(4 downto 0),
        asic_mask          => asic_mask(4 downto 0),
        first_dig_win      => first_dig_win,
        last_dig_win       => last_dig_win,

        -- pedestal data
        ped_fetch_asic_no  => i_ped_fetch_asic_no(0),
        ped_fetch_chan     => ped_fetch_chan(0),
        ped_win_samp_start => ped_win_samp_start(0),
        ped_fetch_ena      => ped_fetch_ena(0),
        ped_fetch_ack      => ped_fetch_ack(0),
        ped_fifo_wr_asic   => ped_fifo_asic_sel,
        ped_fifo_wr_chan   => ped_fifo_chan_sel,
        ped_fifo_wr_ena    => ped_fifo_wr_ena(0),
        ped_fifo_din       => ped_fifo_din,

        -- wires to/from TargetX
        BUS_RD_ENA         => BUSA_RD_ENA,
        BUS_RAMP           => BUSA_RAMP,
        BUS_CLR            => BUSA_CLR,
        BUS_DO             => BUSA_DO,
        SR_CLR             => BUSA_SR_CLEAR,
        SR_CLK             => SR_CLOCK(4 downto 0),
        SR_SEL             => BUSA_SR_SEL,
        BUS_RD_WINSEL      => BUSA_WINSEL,
        SAMPLESEL          => BUSA_SAMPLESEL,
        SAMPLESEL_ANY      => SAMPLESEL_ANY(4 downto 0),

        -- wires to HitDataSerializer
        rx_features_ack    => rx_features_ack(0),
        rx_features_ena    => rx_features_ena(0),
        last_hit           => last_hit(0),
        -- null_hit           => null_hit(0),
        peak               => peak(0),
        le_time            => le_time(0),
        daq_chan           => daq_chan(0),

        -- SCROD config registers
        ramp_length        => wave_config_q6.ramp_length,
        -- force_test_pattern => wave_config_q6.force_test_pattern,
        t_samp_addr_settle => wave_config_q6.t_samp_addr_settle,
        t_setup_ss_any     => wave_config_q6.t_setup_ss_any,
        t_strobe_settle    => wave_config_q6.t_strobe_settle,
        t_sr_clk_high      => wave_config_q6.t_sr_clk_high,
        t_sr_clk_low       => wave_config_q6.t_sr_clk_low,
        t_sr_clk_strobe    => wave_config_q6.t_sr_clk_strobe,
        N_readout_samples  => i_N_readout_samples,
        LE_time_thresh     => wave_config_q6.LE_time_thresh,

        -- status registers
        debug_we           => debug_wave_we(0),
        debug_wave         => debug_wave_din(0),
        DigStoreProcBusy   => DigStoreProcBusy(0),
        DigNShiftBusy      => DigNShiftBusy(0),
        DigBusy            => DigBusy(0),
        ShiftOutWinBusy    => ShiftOutWinBusy(0),
        ShiftOutSampBusy   => ShiftOutSampBusy(0),
        FeatExtBusy        => FeatExtBusy(0),
        PedFetchQueueBusy  => PedFetchQueueBusy(0),

        -- wires for ped calc
        prime_fifos        => prime_fifos,
        summing_ena        => summing_ena,
        avg_peds_ena       => avg_peds_ena,
        avg_peds_busy      => avg_peds_busy(0),
        wr_peds2sram_ena   => wr_peds2sram_ena(0),
        wr_peds2sram_ack   => wr_peds2sram_ack(0),
        even_ped           => even_sample(0),
        odd_ped            => odd_sample(0),
        sram_asic_addr     => sram_asic_addr(0),
        sram_chan_addr     => sram_chan_addr(0),
        sram_samp_addr     => sram_samp_addr(0),
        fe_dbg => wave_stat_i(0).fe_dbg_a,
        sps_reset          => sps_reset_sr(sps_reset_sr'left),
        SPS_hist_rd_addr   => wave_config_q6.SPS_hist_rd_addr(0),
        SPS_hist_rd_data   => SPS_hist_rd_data(0)
);


    busB : entity work.SingleBusProcessing
    generic map (
        N_BITS_AVG_g => N_BITS_AVG_g
    )
    port map (
        -- main inputs
        clk                => clk,
        rst                => busB_reset,
        ped_sub_ena        => wave_config_q6.ped_sub_ena,
        disambig_tb5       => disambig_tb5,
        measure_peds       => wave_config_q6.measure_peds,
        stream_peds        => wave_config_q6.stream_peds,
        ena                => single_bus_ena,
        win_samp_start     => starting_win_samp(9 downto 5),
        trig_bits          => i_trig_bits(9 downto 5),
        asic_mask          => asic_mask(9 downto 5),
        first_dig_win      => first_dig_win,
        last_dig_win       => last_dig_win,

        -- pedestal data
        ped_fetch_asic_no  => i_ped_fetch_asic_no(1),
        ped_fetch_chan     => ped_fetch_chan(1),
        ped_win_samp_start => ped_win_samp_start(1),
        ped_fetch_ena      => ped_fetch_ena(1),
        ped_fetch_ack      => ped_fetch_ack(1),
        ped_fifo_wr_asic   => ped_fifo_asic_sel,
        ped_fifo_wr_chan   => ped_fifo_chan_sel,
        ped_fifo_wr_ena    => ped_fifo_wr_ena(1),
        ped_fifo_din       => ped_fifo_din,

        -- wires to/from TargetX
        BUS_RD_ENA         => BUSB_RD_ENA,
        BUS_RAMP           => BUSB_RAMP,
        BUS_CLR            => BUSB_CLR,
        BUS_DO             => BUSB_DO,
        SR_CLR             => BUSB_SR_CLEAR,
        SR_CLK             => SR_CLOCK(9 downto 5),
        SR_SEL             => BUSB_SR_SEL,
        BUS_RD_WINSEL      => BUSB_WINSEL,
        SAMPLESEL          => BUSB_SAMPLESEL,
        SAMPLESEL_ANY      => SAMPLESEL_ANY(9 downto 5),

        -- wires to HitDataSerializer
        rx_features_ack    => rx_features_ack(1),
        rx_features_ena    => rx_features_ena(1),
        last_hit           => last_hit(1),
        -- null_hit           => null_hit(1),
        peak               => peak(1),
        le_time            => le_time(1),
        daq_chan           => daq_chan(1),

        -- SCROD config registers
        ramp_length        => wave_config_q6.ramp_length,
        -- force_test_pattern => wave_config_q6.force_test_pattern,
        t_samp_addr_settle => wave_config_q6.t_samp_addr_settle,
        t_setup_ss_any     => wave_config_q6.t_setup_ss_any,
        t_strobe_settle    => wave_config_q6.t_strobe_settle,
        t_sr_clk_high      => wave_config_q6.t_sr_clk_high,
        t_sr_clk_low       => wave_config_q6.t_sr_clk_low,
        t_sr_clk_strobe    => wave_config_q6.t_sr_clk_strobe,
        N_readout_samples  => i_N_readout_samples,
        LE_time_thresh     => wave_config_q6.LE_time_thresh,

        -- status registers
        debug_we           => debug_wave_we(1),
        debug_wave         => debug_wave_din(1),
        DigStoreProcBusy   => DigStoreProcBusy(1),
        DigNShiftBusy      => DigNShiftBusy(1),
        DigBusy            => DigBusy(1),
        ShiftOutWinBusy    => ShiftOutWinBusy(1),
        ShiftOutSampBusy   => ShiftOutSampBusy(1),
        FeatExtBusy        => FeatExtBusy(1),
        PedFetchQueueBusy  => PedFetchQueueBusy(1),

        -- wires for ped calc
        prime_fifos        => prime_fifos,
        summing_ena        => summing_ena,
        avg_peds_ena       => avg_peds_ena,
        avg_peds_busy      => avg_peds_busy(1),
        wr_peds2sram_ena   => wr_peds2sram_ena(1),
        wr_peds2sram_ack   => wr_peds2sram_ack(1),
        even_ped           => even_sample(1),
        odd_ped            => odd_sample(1),
        sram_asic_addr     => sram_asic_addr(1),
        sram_chan_addr     => sram_chan_addr(1),
        sram_samp_addr     => sram_samp_addr(1),
        fe_dbg => wave_stat_i(0).fe_dbg_b,
        sps_reset          => sps_reset_sr(sps_reset_sr'left),
        SPS_hist_rd_addr   => wave_config_q6.SPS_hist_rd_addr(1),
        SPS_hist_rd_data   => SPS_hist_rd_data(1)
    );


    ped_fetcher : entity work.PedestalFetcher
    port map (
        clk               => clk,
        rst               => ro_reset,
        ena               => ped_fetch_ena,
        ack               => ped_fetch_ack,
        asic_addr         => i_ped_fetch_asic_no,
        chan_addr         => ped_fetch_chan,
        win_samp_start    => ped_win_samp_start,
        fifo_asic_sel     => ped_fifo_asic_sel, -- fanned out to busA/B, wr_ena controlled
        fifo_chan_sel     => ped_fifo_chan_sel, -- fanned out to busA/B, wr_ena controlled
        ped_fifo_wr_ena   => ped_fifo_wr_ena,   -- slv[1:0]
        ped_fifo_din      => ped_fifo_din,
        N_readout_samples => i_N_readout_samples,
        RAM_do            => RAM_do,
        RAM_ADDR          => RAM_rd_addr
    );


    ped_writer : entity work.PedestalWriter
    port map (
        clk           => clk,
        ena           => wr_peds2sram_ena,
        ack           => wr_peds2sram_ack,
        chan_addr     => sram_chan_addr,
        asic_addr     => sram_asic_addr,
        samp_addr     => sram_samp_addr,
        win_addr      => ped_meas_win,
        even_sample   => even_sample,
        odd_sample    => odd_sample,
        RAM_din       => i_RAM_din,
        RAM_WEb       => i_RAM_WEb,
        RAM_ADDR      => RAM_wr_addr
    );


    ped_measure : entity work.MeasurePeds
    generic map (
        LAST_WINDOW_ADDRESS => LAST_WINDOW_ADDRESS,
        N_BITS_AVG_g => N_BITS_AVG_g
    )
    port map (
        clk                 => clk,
        ena                 => meas_peds_ena,
        busy                => wave_stat_i(0).ped_meas_busy,
        force_trig          => ped_start_ro,
        trig_win            => ped_meas_win,
        prime_fifos         => prime_fifos,
        summing_ena         => summing_ena,
        cur_win             => cur_win,
        either_bus_busy     => either_bus_busy,
        avg_peds_ena        => avg_peds_ena,
        avg_peds_busy       => avg_peds_busy,
        dig_busy            => or_dig_busy--,
        -- bus_mask            => ped_bus_mask
    );


   HitData_Serializer_i : entity work.KLMHitDataSerializer
   port map(
      clk          => clk,
      rst          => i_b2tt_runreset(i_b2tt_runreset'left),
      run          => ser_run,

      -- daq data to be serialized
      first_hit    => HitData.first_hit, -- hit is the first hit in the event
      last_hit     => HitData.last_hit,  -- hit is the last hit in the event
      null_hit     => HitData.null_hit,  -- hit is null
      word1        => HitData.word1,     -- in
      word2        => HitData.word2,     -- in
      word3        => HitData.word3,     -- in
      word4        => HitData.word4,     -- in

      -- nxt        => nxt,
      fifo_empty   => qt_fifo_empty,
      -- fifo_full  => open,
      fifo_dout    => qt_fifo_dout,
      fifo_ren     => qt_fifo_rd_en,
      fifo_err_cnt => qt_fifo_err_cnt,
      busy         => ser_busy
   );


   tristate : for i in 0 to 7 generate
      sda_buff: IOBUF 
         -- generic map(IFD_DELAY_VALUE => "0", DRIVE => 12, SLEW => "SLOW") <-- Default values, uncomment and change if needed
         port map(o => RAM_do(i), io => RAM_IO(i), i => RAM_din(i), t => RAM_rw);
   end generate;


end Behavioral;