PedestalWriter.vhd

-- Module Name:    PedestalWriter - Behavioral
-- Create Date:    11:07:41 09/21/2018
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
use IEEE.STD_LOGIC_MISC.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
Library work;
use work.klm_scint_pkg.all;

entity PedestalWriter is
    Generic (
        -- PED_RAM_tSCE_g     : integer := 7; -- 55 ns -- setup chip ena (min 40 ns)
        PED_RAM_tSCE_g     : integer := 6; -- 40 ns -- setup chip ena (min 40 ns)
        PED_RAM_tLZWE_g    : integer := 20; -- 16 ns -- WEb high to low Z (min 10 ns)
        PED_RAM_tSA_g      : integer := 1; -- 8 ns -- setup addr (min 0 ns)
        PED_RAM_tHA_g      : integer := 1  -- 8 ns -- hold addr (min 0 ns)
    );
    Port (
        clk                : in  STD_logic;
        ena                : in  std_logic_vector(1 downto 0) := (others => '0');
        ack                : out std_logic_vector(1 downto 0) := (others => '0');
        -- initial address
        asic_addr          : in  slv3(1 downto 0);-- := (others => "000");
        chan_addr          : in  slv4(1 downto 0) := (others => "0000");
        win_addr           : in  std_logic_vector(8 downto 0) := (others => '0');
        samp_addr          : in  slv4(1 downto 0) := (others => (others=>'0'));
        -- sample data
        even_sample        : in  slv12(1 downto 0) := (others => (others=>'0'));
        odd_sample         : in  slv12(1 downto 0) := (others => (others=>'0'));
        -- ped_wr_state       : out std_logic_vector(1 downto 0);
        --PedRAM pins
        RAM_din            : out std_logic_vector(7 downto 0) := (others => '0');
        RAM_WEb            : out std_logic := '1';
        -- RAM_OEb            : out std_logic := '0';
        RAM_ADDR           : out std_logic_vector(21 downto 0) := (others => '1')
    );
end PedestalWriter;

architecture Behavioral of PedestalWriter is


    type pedestal_writing_machine is (
        IDLE,
        WRITE_TO_SRAM,
        CHECK_DONE
    );
    signal ped_write_state : pedestal_writing_machine := IDLE;


    signal addr         : slv22(1 downto 0) := (others => "0000000000000000000000"); -- initial address
    -- signal ack_i        : std_logic_vector(1 downto 0) := "00"; -- remember last bus serviced for arbitration reasons
    signal tx_dc        : slv4(1 downto 0) := (others => "0000"); -- daughter card number for each bus
    signal pedarr       : slv8(2 downto 0) := (others => "00000000");
    signal next_addr    : std_logic_vector(21 downto 0) := (others => '0');

    constant ram_sce_strobe : std_logic_vector(PED_RAM_tSCE_g - 1 downto 0) := (others => '0');
    signal ram_web_i : std_logic_vector(PED_RAM_tSCE_g - 1  downto 0) := (others => '1');
    signal load_RAM_WEb_strobe : std_logic := '0';

begin

    tx_dc(0) <= '0' & asic_addr(0);
    tx_dc(1) <= ('0' & asic_addr(1)) + "0101";

    addr(0) <= tx_dc(0) & chan_addr(0) & win_addr & samp_addr(0) & "0";  -- samp start must always be even
    addr(1) <= tx_dc(1) & chan_addr(1) & win_addr & samp_addr(1) & "0";  -- samp start must always be even

    -- pack (here):  pedarr(0) <= even_sample(*)(11 downto 4);
    -- pack (here):  pedarr(1) <= even_sample(*)(3 downto 0) & odd_sample(*)(11 downto 8);
    -- pack (here):  pedarr(2) <= odd_sample(*)(7 downto 0);
    -- unpack:  even_sample <= pedarr(0) & pedarr(1)(7 downto 4);
    -- unpack:  odd_sample  <= pedarr(1)(3 downto 0) & pedarr(2);

    ce_shift_reg : process(clk, RAM_WEb_i, load_RAM_WEb_strobe)
    begin
        if rising_edge(clk) then
            if load_RAM_WEb_strobe = '1' then
                RAM_WEb_i <= ram_sce_strobe;
            else
                RAM_WEb_i <= RAM_WEb_i(RAM_WEb_i'left - 1 downto 0) & '1';
            end if;
        end if;
    end process;
    RAM_WEb <= RAM_WEb_i(RAM_WEb_i'left);

    write_one_window_of_peds : process(clk, ena, pedarr, addr, next_addr)
        variable byte_cnt : integer range 0 to 2 := 0; -- count groups of 3 adddresses
        variable timer : integer range 0 to (PED_RAM_tSCE_g + PED_RAM_tLZWE_g) := 0;
    begin
        if (rising_edge(clk)) then
            case ped_write_state is

                when IDLE =>
                    -- ped_wr_state <= "00";
                    byte_cnt := 0;
                    timer := 0;
                    ack <= "00";
                    -- unfair arbiter (biased toward bus 0)
                    if ena(0) = '1' then
                        ack <= "01";
                        next_addr <= addr(0) + ("0" & addr(0)(21 downto 1));  -- easy 1.5x for even numbers only!
                        pedarr(0) <= even_sample(0)(11 downto 4);
                        pedarr(1) <= even_sample(0)(3 downto 0) & odd_sample(0)(11 downto 8);
                        pedarr(2) <= odd_sample(0)(7 downto 0);
                    elsif ena(1) = '1' then
                        ack <= "10";
                        next_addr <= addr(1) + ("0" & addr(1)(21 downto 1));
                        pedarr(0) <= even_sample(1)(11 downto 4);
                        pedarr(1) <= even_sample(1)(3 downto 0) & odd_sample(1)(11 downto 8);
                        pedarr(2) <= odd_sample(1)(7 downto 0);
                    end if;
                    if (ena(0) or ena(1)) = '1' then
                        load_RAM_WEb_strobe <= '1';
                        ped_write_state <= WRITE_TO_SRAM;
                    else
                        ped_write_state <= IDLE;
                    end if;


                When WRITE_TO_SRAM =>
                    -- ped_wr_state <= "01";
                    load_RAM_WEb_strobe <= '0';
                    if timer > 1 then
                        ack <= "00";
                    end if;
                    RAM_ADDR <= next_addr;
                    RAM_din <= pedarr(byte_cnt);
                    if timer < (PED_RAM_tSCE_g + PED_RAM_tLZWE_g - 1) then
                        timer := timer + 1;
                        ped_write_state <= WRITE_TO_SRAM;
                    else
                        timer := 0;
                        ped_write_state <= CHECK_DONE;
                    end if;


                When CHECK_DONE =>
                    -- ped_wr_state <= "10";
                    if byte_cnt < 2 then
                        byte_cnt := byte_cnt + 1;
                        next_addr <= next_addr + "0000000000000000000001";
                        load_RAM_WEb_strobe <= '1';
                        ped_write_state <= WRITE_TO_SRAM;
                    else
                        byte_cnt := 0;
                        ped_write_state <= IDLE;
                    end if;

            end case;
        end if;
    end process;



end Behavioral;