Processes
ppln_stat	( clk , wave_stat_i )
conf_dffs	( clk , wave_config , wave_config_q1 , wave_config_q2 , wave_config_q3 , wave_config_q4 , wave_config_q5 )
rst_buff	( clk , b2tt_runreset , i_b2tt_runreset )
busy_lgc	( clk , or_busy_status , queue_full )
trg_buff	( clk , localtrg )
force_trig_buffer	( clk , force_trig )
sps_reset_buffer	( clk , sps_reset )
SRAM_mux	( clk , wave_config_q6.measure_peds , force_trig_sr , i_RAM_din , RAM_wr_addr , RAM_rd_addr , i_RAM_WEb )
ena_logic	( clk , ped_start_ro , daq_start_ro )
asic_chan_win_mux	( clk , wave_config_q6.measure_peds , ped_meas_win , daq_asic_mask , trig_q0 )
trg_proc	( clk , i_localtrg (i_localtrg 'left) , queue_full , mask_ack , trig )
trg_queue	( clk , i_b2tt_runreset , trig_queue_wr_ena , queue_full , queue_empty , hit_bldr_fsm_busy , trig_in_t1 )
mask_unmask_proc	( clk , mask_windows , unmask_windows , trig_in_t1 .first_dig_win , trig_q0.first_dig_win )
hit_bldr	( clk , i_b2tt_runreset , start_readout , trig_q0 , rx_features_ena , peak , le_time , daq_chan , i_full_proc_cnt , i_simp_proc_cnt , i_null_proc_cnt , last_hit , unmask_ack , wave_config_q6.use_ftsw_trig , queue_above_thresh )
ppln_hit_data	( clk , daq_axis_i , daq_chan_i , trig_q0.ctime , simp , TB5 , le_time_i , peak_i , HitData_i , ser_run_i )

Types
trig_staging_FSM	( IDLE , WAIT_VALID , PROCESSING_REQ , WAIT_ACK )
modify_sampling_mask_FSM	( IDLE , WAIT_DONE )
ro_states	( IDLE , WAIT_RESET , CHECK_VALID , WAIT_WAVEFORM_READOUT , SEND_HITS , CHECK_DONE , STOP , SEND_SIMPLE )

Signals
wave_stat_i	wave_stat_vec ( SLC_STAT_BUFF_DEPTH_g- 1 downto 0 ) := ( others = > wave_stat_0 )
	ppln_stat:
wave_config_q1	wave_config_t := default_wave_config
	conf_dffs:
wave_config_q2	wave_config_t := default_wave_config
wave_config_q3	wave_config_t := default_wave_config
wave_config_q4	wave_config_t := default_wave_config
wave_config_q5	wave_config_t := default_wave_config
wave_config_q6	wave_config_t := default_wave_config
i_b2tt_runreset	std_logic_vector ( reset_buff_depth_g- 1 downto 0 )
	rst_buff:
busA_reset	std_logic := ' 0 '
busB_reset	std_logic := ' 0 '
or_busy_sr	std_logic_vector ( 5 downto 0 ) := ( others = > ' 0 ' )
	busy_lgc:
either_bus_busy	std_logic := ' 0 '
i_localtrg	std_logic_vector ( TRG_BUFF_DEPTH_g- 1 downto 0 )
	trg_buff:
force_trig_sr	std_logic_vector ( FORCE_TRIG_BUF_DEPTH_g- 1 downto 0 ) := ( others = > ' 0 ' )
	force_trig_buffer:
sps_reset_sr	std_logic_vector ( FORCE_TRIG_BUF_DEPTH_g- 1 downto 0 ) := ( others = > ' 0 ' )
meas_peds_ena	std_logic
	SRAM_mux:
i_N_readout_samples	std_logic_vector ( 7 downto 0 ) := " 00100000 "
i_RAM_WEb	std_logic := ' 1 '
i_RAM_din	std_logic_vector ( 7 downto 0 ) := ( others = > ' 0 ' )
RAM_din	std_logic_vector ( 7 downto 0 ) := ( others = > ' 0 ' )
RAM_rw	std_logic := ' 1 '
single_bus_ena	std_logic := ' 0 '
	ena_logic:
SPS_measure_start	std_logic_vector ( 1 downto 0 ) := " 00 "
i_trig_bits	slv5 ( 9 downto 0 ) := ( others = > ( others = > ' 0 ' ) )
	asic_chan_win_mux:
starting_win_samp	slv14 ( 9 downto 0 ) := ( others = > ( others = > ' 0 ' ) )
first_dig_win	std_logic_vector ( 8 downto 0 ) := ( others = > ' 0 ' )
last_dig_win	std_logic_vector ( 8 downto 0 ) := ( others = > ' 0 ' )
asic_mask	std_logic_vector ( 9 downto 0 ) := ( others = > ' 0 ' )
trig_staging	trig_staging_FSM := IDLE
	trg_proc:
trig_in_t0	trig_info_type_0 := null_trig_info_t0
	copy of input trig without ROI
calc_roi_ena	std_logic := ' 0 '
trg_proc_busy	std_logic := ' 0 '
mask_windows	std_logic := ' 0 '
trig_queue_wr_ena	std_logic := ' 0 '
wr_ptr	integer range 0 to TRIG_QUEUE_DEPTH_g- 1 := 0
	trg_queue:
rd_ptr	integer range 0 to TRIG_QUEUE_DEPTH_g- 1 := 0
wr_ptr_nxt	integer range 0 to TRIG_QUEUE_DEPTH_g- 1 := 0
rd_ptr_nxt	integer range 0 to TRIG_QUEUE_DEPTH_g- 1 := 0
queue_empty	std_logic := ' 1 '
queue_above_thresh	std_logic := ' 0 '
queue_full	std_logic := ' 0 '
start_readout	std_logic := ' 0 '
trig_queue	trig_queue_type ( TRIG_QUEUE_DEPTH_g- 1 downto 0 ) := ( others = > null_trig_info_t1 )
trig_q0	trig_info_type_1 := null_trig_info_t1
modify_sampling_mask	modify_sampling_mask_FSM := IDLE
	mask_unmask_proc:
mask_ack	std_logic := ' 0 '
unmask_ack	std_logic := ' 0 '
i_ana_wr_ena_mask	TARGETX_analong_wr_ena_mask_t := null_TX_ana_wr_ena_mask
ro_state	ro_states := IDLE
	hit_bldr:
hit_bldr_fsm_busy	std_logic := ' 0 '
ro_reset	std_logic := ' 0 '
daq_axis_i	std_logic := ' 0 '
daq_chan_i	std_logic_vector ( 6 downto 0 ) := ( others = > ' 0 ' )
daq_chan_base	std_logic_vector ( 6 downto 0 ) := ( others = > ' 0 ' )
tb5	std_logic := ' 0 '
simp	std_logic := ' 0 '
le_time_i	std_logic_vector ( 13 downto 0 ) := ( others = > ' 0 ' )
peak_i	std_logic_vector ( 11 downto 0 ) := ( others = > ' 0 ' )
daq_start_ro	std_logic := ' 0 '
i_full_proc_cnt	std_logic_vector ( 15 downto 0 ) := ( others = > ' 0 ' )
i_simp_proc_cnt	std_logic_vector ( 15 downto 0 ) := ( others = > ' 0 ' )
i_null_proc_cnt	std_logic_vector ( 15 downto 0 ) := ( others = > ' 0 ' )
daq_asic_mask	std_logic_vector ( 9 downto 0 ) := ( others = > ' 0 ' )
simp_asic_mask	std_logic_vector ( 9 downto 0 ) := ( others = > ' 0 ' )
unmask_windows	std_logic := ' 0 '
rx_features_ack	std_logic_vector ( 1 downto 0 ) := ( others = > ' 0 ' )
ser_run_i	std_logic := ' 0 '
HitData_i	KlmScrodHitDataType := KlmScrodHitDataNull
ser_run	std_logic := ' 0 '
	ppln_hit_data:
HitData	KlmScrodHitDataType := KlmScrodHitDataNull
or_dig_busy	std_logic := ' 0 '
	ASYNCHRONOUSLY DRIVEN SIGNALS.
single_bus_reset	std_logic := ' 0 '
disambig_tb5	std_logic := ' 1 '
or_busy_status	std_logic := ' 0 '
trig_in_t1	trig_info_type_1 := null_trig_info_t1
	CALC_ROI:
i_ped_fetch_asic_no	slv3 ( 1 downto 0 )
	busA/busB:
ped_fetch_chan	slv4 ( 1 downto 0 ) := ( others = > " 0000 " )
ped_win_samp_start	slv14 ( 1 downto 0 ) := ( others = > ( others = > ' 0 ' ) )
ped_fetch_ena	std_logic_vector ( 1 downto 0 ) := ( others = > ' 0 ' )
BUSA_WINSEL	std_logic_vector ( 8 downto 0 ) := ( others = > ' 0 ' )
BUSB_WINSEL	std_logic_vector ( 8 downto 0 ) := ( others = > ' 0 ' )
rx_features_ena	std_logic_vector ( 1 downto 0 ) := ( others = > ' 0 ' )
last_hit	std_logic_vector ( 1 downto 0 ) := " 00 "
peak	slv12 ( 1 downto 0 ) := ( others = > " 000000000000 " )
le_time	slv14 ( 1 downto 0 ) := ( others = > " 00000000000000 " )
daq_chan	slv7 ( 1 downto 0 ) := ( others = > " 0000000 " )
DigStoreProcBusy	std_logic_vector ( 1 downto 0 ) := " 00 "
DigNShiftBusy	std_logic_vector ( 1 downto 0 ) := " 00 "
DigBusy	std_logic_vector ( 1 downto 0 ) := " 00 "
ShiftOutWinBusy	std_logic_vector ( 1 downto 0 ) := " 00 "
ShiftOutSampBusy	std_logic_vector ( 1 downto 0 ) := " 00 "
FeatExtBusy	std_logic_vector ( 1 downto 0 ) := " 00 "
PedFetchQueueBusy	std_logic_vector ( 1 downto 0 ) := " 00 "
avg_peds_busy	std_logic_vector ( 1 downto 0 ) := " 00 "
wr_peds2sram_ena	std_logic_vector ( 1 downto 0 ) := ( others = > ' 0 ' )
even_sample	slv12 ( 1 downto 0 ) := ( others = > ( others = > ' 0 ' ) )
odd_sample	slv12 ( 1 downto 0 ) := ( others = > ( others = > ' 0 ' ) )
sram_asic_addr	slv3 ( 1 downto 0 ) := ( others = > ( others = > ' 0 ' ) )
sram_chan_addr	slv4 ( 1 downto 0 ) := ( others = > ( others = > ' 0 ' ) )
sram_samp_addr	slv4 ( 1 downto 0 ) := ( others = > ( others = > ' 0 ' ) )
ped_fetch_ack	std_logic_vector ( 1 downto 0 ) := ( others = > ' 0 ' )
	ped_fetcher:
ped_fifo_asic_sel	std_logic_vector ( 4 downto 0 ) := ( others = > ' 0 ' )
ped_fifo_chan_sel	std_logic_vector ( 3 downto 0 ) := ( others = > ' 0 ' )
ped_fifo_wr_ena	std_logic_vector ( 1 downto 0 ) := ( others = > ' 0 ' )
ped_fifo_din	std_logic_vector ( 11 downto 0 ) := ( others = > ' 0 ' )
RAM_rd_addr	std_logic_vector ( 21 downto 0 ) := ( others = > ' 0 ' )
RAM_wr_addr	std_logic_vector ( 21 downto 0 ) := ( others = > ' 0 ' )
	ped_writer:
wr_peds2sram_ack	std_logic_vector ( 1 downto 0 ) := ( others = > ' 0 ' )
ped_meas_win	std_logic_vector ( 8 downto 0 ) := ( others = > ' 0 ' )
	ped_measure:
ped_start_ro	std_logic := ' 0 '
prime_fifos	std_logic := ' 0 '
avg_peds_ena	std_logic := ' 0 '
summing_ena	std_logic := ' 0 '
ser_busy	std_logic := ' 0 '
RAM_do	std_logic_vector ( 7 downto 0 ) := ( others = > ' 0 ' )
	sda_buff:

Instantiations
calc_roi	CalculateROI <Entity CalculateROI>
busa	SingleBusProcessing <Entity SingleBusProcessing>
busb	SingleBusProcessing <Entity SingleBusProcessing>
ped_fetcher	PedestalFetcher <Entity PedestalFetcher>
ped_writer	PedestalWriter <Entity PedestalWriter>
ped_measure	MeasurePeds <Entity MeasurePeds>
hitdata_serializer_i	KLMHitDataSerializer <Entity KLMHitDataSerializer>
sda_buff	iobuf

Detailed Description

Definition at line 161 of file WaveformReadout.vhd.

The documentation for this class was generated from the following file:

klm_scint/source/WaveformReadout.vhd

Processes

Types

Signals

Instantiations

Detailed Description