PedestalFetcher.vhd

-- Module Name:    PedestalFetcher - Behavioral
-- Create Date:    11:07:41 09/21/2018
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
use IEEE.STD_LOGIC_MISC.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
Library work;
use work.klm_scint_pkg.all;


entity PedestalFetcher is
    Generic (
        ped_ram_tAA        : integer range 0 to 15 := 9 --(71 ns @ 127 MHz) : spec 55 ns
    );
    Port (
        clk                : in  STD_logic;
        rst                : in  STD_logic;
        ena                : in  std_logic_vector(1 downto 0) := (others => '0');
        ack                : out std_logic_vector(1 downto 0) := (others => '0');
        -- initial address
        asic_addr          : in  slv3(1 downto 0);-- := (others => "000");
        chan_addr          : in  slv4(1 downto 0) := (others => "0000");
        win_samp_start     : in  slv14(1 downto 0) := (others => (others=>'0') );
        -- wires with storage FIFOs
        fifo_asic_sel      : out std_logic_vector(4 downto 0) := (others => '0');
        fifo_chan_sel      : out std_logic_vector(3 downto 0) := (others => '0');
        ped_fifo_wr_ena    : out std_logic_vector(1 downto 0) := (others => '0');
        ped_fifo_din       : out std_logic_vector(11 downto 0) := (others => '0');
        -- control registers
        N_readout_samples  : in  std_logic_vector(7 downto 0);
        --PedRAMaccess signals
        RAM_do             : in  std_logic_vector(7 downto 0);
        RAM_ADDR           : out std_logic_vector(21 downto 0) := (others => '1')
    );
end PedestalFetcher;

architecture Behavioral of PedestalFetcher is


    type pedestal_fetching_machine is (
        IDLE,
        PREPARING_NEXT_ADDR,
        WAITING_TAA,
        RESETTING
    );
    signal ped_fetch_state : pedestal_fetching_machine := IDLE;

    type xfer_to_fifo_machine is (
        IDLE,
        WRITE_NEXT_VAL,
        FINISHING
    );
    signal fifo_fill_state : xfer_to_fifo_machine := IDLE;

    signal addr_MSBYTE  : std_logic_vector(7 downto 0) := (others => '0'); -- initial address 8 MSBs
    signal addr         : slv22(1 downto 0) := (others => "0000000000000000000000"); -- initial address
    signal next_addr    : std_logic_vector(21 downto 0) := (others => '0');
    signal nxt_wn_smp   : std_logic_vector(13 downto 0) := (others => '0'); -- count over ROI
    signal ped_asic_i   : std_logic_vector(4 downto 0);
    signal ped_ch_i     : std_logic_vector(3 downto 0);
    signal count3       : integer range 0 to 3 := 0; -- count groups of 3 adddresses
    signal pedarr       : slv8(2 downto 0) := (others => "00000000"); -- local storage for 3 consecutive ram outputs
    signal xfer_to_fifo : std_logic := '0'; -- enable signal for xfer_to_fifo state machine
    signal start_rx     : std_logic := '0'; -- enable signal for SRAM_rx process
    signal ack_i        : std_logic_vector(1 downto 0) := "00"; -- remember last bus serviced for arbitration reasons
    signal ack_ii       : std_logic_vector(1 downto 0) := "00"; -- remember last bus serviced for arbitration reasons
    signal ack_prev     : std_logic_vector(1 downto 0) := "01"; -- remember last bus serviced for arbitration reasons
    signal tx_dc        : slv4(1 downto 0) := (others => "0000"); -- daughter card number for each bus
    signal idx : integer range 0 to 2;

begin

    ack <= ack_i;

    tx_dc(0) <= '0' & asic_addr(0);
    tx_dc(1) <= "0101" + ('0' & asic_addr(1));

    addr(0) <= tx_dc(0) & chan_addr(0) & win_samp_start(0)(13 downto 1) & '0';
    addr(1) <= tx_dc(1) & chan_addr(1) & win_samp_start(1)(13 downto 1) & '0';
    
--------------------------------------------------------------------------------
--  Read ext. SRAM using address-transition-controled mode
--------------------------------------------------------------------------------
    SRAM_tx : process(clk)
        variable samp_cnt : std_logic_vector(7 downto 0);
        variable count_tAA    : integer range 0 to 15 := 0;
    begin
        if (rising_edge(clk)) then
            if rst = '1' then
                ped_fetch_state <= IDLE;
            else
                
                case ped_fetch_state is

                    when IDLE =>
                        idx <= 0;
                        samp_cnt := "00000000";
                        nxt_wn_smp <= (others=>'0');
                        ped_asic_i <= (others=>'0');
                        count_tAA := 0;
                        
                        -- Single bus enable
                        if (ena(0) xor ena(1)) = '1' then
                            ack_i <= ena;
                            if ena(0) = '1' then
                                addr_MSBYTE <= addr(0)(21 downto 14);
                                RAM_ADDR <= addr(0) + ('0' & addr(0)(21 downto 1));
                                next_addr <= addr(0) + ('0' & addr(0)(21 downto 1)) + "0000000000000000000001";
                                nxt_wn_smp <= win_samp_start(0) + "10";
                                ped_asic_i(to_integer(unsigned(asic_addr(0)))) <= '1';
                                ped_ch_i <= chan_addr(0);
                            else
                                addr_MSBYTE <= addr(1)(21 downto 14);
                                RAM_ADDR <= addr(1) + ('0' & addr(1)(21 downto 1));
                                next_addr <= addr(1) + ('0' & addr(1)(21 downto 1)) + "0000000000000000000001";
                                nxt_wn_smp <= win_samp_start(1) + "10";
                                ped_asic_i(to_integer(unsigned(asic_addr(1)))) <= '1';
                                ped_ch_i <= chan_addr(1);
                            end if;
                        -- Arbiter for collisions between busses
                        elsif (ena(0) and ena(1)) = '1' then
                            ack_i <= not ack_prev;
                            if ack_prev(0) = '1' then
                                addr_MSBYTE <= addr(1)(21 downto 14);
                                RAM_ADDR <= addr(1) + ('0' & addr(1)(21 downto 1));
                                next_addr <= addr(1) + ('0' & addr(1)(21 downto 1)) + "0000000000000000000001";
                                nxt_wn_smp <= win_samp_start(1) + "00000000000010";
                                ped_asic_i(to_integer(unsigned(asic_addr(1)))) <= '1';
                                ped_ch_i <= chan_addr(1);
                            else
                                addr_MSBYTE <= addr(0)(21 downto 14);
                                RAM_ADDR <= addr(0) + ('0' & addr(0)(21 downto 1));
                                next_addr <= addr(0) + ('0' & addr(0)(21 downto 1)) + "0000000000000000000001";
                                nxt_wn_smp <= win_samp_start(0) + "00000000000010";
                                ped_asic_i(to_integer(unsigned(asic_addr(0)))) <= '1';
                                ped_ch_i <= chan_addr(0);
                            end if;
                        else
                            ack_i <= "00";
                        end if;
                        if (ena(0) or ena(1)) = '1' then
                            start_rx <= '1';
                            count3 <= 0;
                            ped_fetch_state <= PREPARING_NEXT_ADDR;
                        else
                            ped_fetch_state <= IDLE;
                        end if;

                    when PREPARING_NEXT_ADDR =>
                        start_rx <= '0';
                        if samp_cnt < N_readout_samples then
                            ped_fetch_state <= WAITING_TAA;
                            count3 <= 0;
                        else
                            ack_prev <= ack_i;
                            ped_fetch_state <= RESETTING;
                        end if;

                    -- wait time 55 ns for address-transition-controlled mode
                    when WAITING_TAA =>
                        start_rx <= '0';
                        if count_tAA < ped_ram_tAA then
                            count_tAA := count_tAA + 1;
                            ped_fetch_state <= WAITING_TAA;
                        else -- data ready
                            -- scheme of 2 peds in 3 addresses handled here.
                            RAM_ADDR <= next_addr; -- if last sample done, read next anyway, it would be good that we wait 55 ns to return to IDLE so fifo xfer can finis
                            start_rx <= '1';
                            idx <= count3;
                            if count3 /= 1 then
                                next_addr <= next_addr + "0000000000000000000001";
                            else    
                                next_addr <= (addr_MSBYTE & nxt_wn_smp(13 downto 0)) + ("0" & addr_MSBYTE & nxt_wn_smp(13 downto 1));
                                nxt_wn_smp <= nxt_wn_smp + "00000000000010";
                            end if;
                            if count3 < 2 then
                                count_tAA := 1; -- start counting on address transition.
                                count3 <= count3 + 1;
                                ped_fetch_state <= WAITING_TAA;
                            else
                                ack_ii <= ack_i;
                                count_tAA := 2; -- start counting on address transition.
                                count3 <= 0;
                                samp_cnt := samp_cnt + "00000010";
                                ped_fetch_state <= PREPARING_NEXT_ADDR;
                            end if;
                        end if;
                        
                    when RESETTING =>
                        if count_tAA < ped_ram_tAA then
                            count_tAA := count_tAA + 1;
                            ped_fetch_state <= RESETTING;
                        else -- data ready
                            ped_fetch_state <= IDLE;
                        end if;
                end case;
            end if;
        end if;
    end process;

    SRAM_rx : process(clk, start_rx, idx, RAM_do)
        variable start_rx_shift : std_logic_vector(ped_ram_tAA downto 0);
    begin
        if rising_edge(clk) then
            xfer_to_fifo <= '0';
            start_rx_shift := start_rx_shift(ped_ram_tAA - 1 downto 0) & start_rx;
            if start_rx_shift(start_rx_shift'left) = '1' then
                pedarr(idx) <= RAM_do;
            end if;
            if start_rx_shift(start_rx_shift'left) = '1' and idx = 2 then
                xfer_to_fifo <= '1';
            end if;
        end if;
    end process;

    -- pack:  pedarr(0) <= even_sample(*)(11 downto 4);
    -- pack:  pedarr(1) <= even_sample(*)(3 downto 0) & odd_sample(*)(11 downto 8);
    -- pack:  pedarr(2) <= odd_sample(*)(7 downto 0);
    -- unpack(here):  even_sample <= pedarr(0) & pedarr(1)(7 downto 4);
    -- unpack(here):  odd_sample  <= pedarr(1)(3 downto 0) & pedarr(2);
    moving_peds_to_fifos : process(clk, xfer_to_fifo, ack_ii, ped_asic_i, ped_ch_i, pedarr)
    begin
        if (rising_edge(clk)) then
            case fifo_fill_state is
                when IDLE =>
                    if xfer_to_fifo = '0' then
                        fifo_fill_state <= IDLE;
                    else
                        ped_fifo_wr_ena <= ack_ii;
                        fifo_asic_sel <= ped_asic_i;
                        fifo_chan_sel <= ped_ch_i;
                        ped_fifo_din <= pedarr(0) & pedarr(1)(7 downto 4);
                        fifo_fill_state <= WRITE_NEXT_VAL;
                    end if;

                when WRITE_NEXT_VAL =>
                    ped_fifo_din <= pedarr(1)(3 downto 0) & pedarr(2);
                    fifo_fill_state <= FINISHING;

                when FINISHING =>
                    ped_fifo_wr_ena <= "00";
                    fifo_fill_state <= IDLE;

            end case;
        end if;
    end process;




end Behavioral;