KLMHitDataSerializer.vhd

library ieee;
    use ieee.std_logic_1164.all;
    use ieee.numeric_std.all;
    use ieee.std_logic_unsigned.all;


entity KLMHitDataSerializer is
   port(
      clk       : in  std_logic;
      rst       : in  std_logic;

      run       : in  std_logic; -- 1) set high for one clock cycle to start single transaction 
                                 --    event ready signal should be sent when all hits are stored in the fifo
                                 -- 2) keep high in streaming mode.
                                 --    event resdy signal may be sent at the same time 
                    
      first_hit : in std_logic;  -- '1' if hit is first in the packet
      last_hit  : in std_logic;  -- '1' if hit is last hit in the packet

      null_hit  : in  std_logic; -- hit data is empty (first_hit and last_hit - don't care)

      -- nxt       : out std_logic; -- ready to accept next hit data

      -- 4 words now TODO:implement actual data format here
      word1     : in  std_logic_vector(15 downto 0);
      word2     : in  std_logic_vector(15 downto 0);
      word3     : in  std_logic_vector(15 downto 0);
      word4     : in  std_logic_vector(15 downto 0);

      -- fifo ports
      fifo_ren   : in  std_logic;
      fifo_empty : out std_logic;
      -- fifo_full  : out std_logic; -- xst653: is used but never assigned
      fifo_dout  : out std_logic_vector(17 downto 0);

      fifo_err_cnt : out std_logic_vector(15 downto 0);

      -- serialization is in progress
      busy         : out std_logic
   );
end KLMHitDataSerializer;

architecture beh of KLMHitDataSerializer is

   signal i_busy      : std_logic;

   -- headers for first and last words in the packet |eof_n|sof_n|
   signal hdr_first   : std_logic_vector(1 downto 0);
   signal hdr_last    : std_logic_vector(1 downto 0);
   
   -- fifo signals
   signal qt_wr_en    : std_logic;
   signal qt_fifo_din : std_logic_vector(17 downto 0); 

   type hit_states is ( IDLE, INI, SEND_WORD1, SEND_WORD2, SEND_WORD3, SEND_WORD4, SEND_NULL );
   signal state       : hit_states := IDLE;

   signal word1_r     : std_logic_vector(15 downto 0);
   signal word2_r     : std_logic_vector(15 downto 0);
   signal word3_r     : std_logic_vector(15 downto 0);
   signal word4_r     : std_logic_vector(15 downto 0);

   signal i_qt_fifo_err_cnt : std_logic_vector(15 downto 0) := (others=>'0');
   signal i_qt_fifo_full    : std_logic;
   signal i_qt_fifo_full_r  : std_logic;

begin
   ------------------------------------------------
   --- FIFO for DAQ data to be sent
   ------------------------------------------------
   -- FIXME move it to readout module
   qtfifo_i : entity work.fifo_cc
   generic map(
      DATA_WIDTH => 18,
      DEPTH      => 8   -- was 13bit = 8192
   )
   port map (
      clk    => clk,
      rst    => rst,
      din    => qt_fifo_din,
      wen    => qt_wr_en,
      ren    => fifo_ren,
      dout   => fifo_dout,
      full   => i_qt_fifo_full,
      empty  => fifo_empty
   );
   ------------------------------------------------
   

   hdr_first <= '1' & (not first_hit);
   hdr_last  <= (not last_hit) & '1';


   SEND_DATA_PROC : process(clk)
   begin
      if rising_edge(clk) then
         if rst = '1' then
            state <= IDLE;
         else 
            -- nxt <= '0';
            
            case state is

               when IDLE => 
                  if run = '1' then
                     if null_hit = '1' then
                        state   <= SEND_NULL;
                     else
                        state   <= INI;
                     end if;
                     i_busy  <= '1';
                     
                     -- nxt <= '1';
                  else
                     state    <= IDLE;
                     i_busy   <= '0';
                     qt_wr_en <= '0';
                  end if;

               when INI =>
                  state   <= SEND_WORD1;
                  word1_r <= word1;
                  word2_r <= word2;
                  word3_r <= word3;
                  word4_r <= word4;

               when SEND_WORD1 =>


                  -- i_busy <= '1';
                  qt_wr_en      <= '1';
                  qt_fifo_din   <= hdr_first & word1_r; 
                  state         <= SEND_WORD2;
                  -- if last_hit = '0' and run = '1' then
                  --    nxt <= '1';
                  -- end if;
            
               when SEND_WORD2 =>
                  qt_fifo_din   <= B"11" & word2_r;
                  state         <= SEND_WORD3;
               
               when SEND_WORD3 =>
                  qt_fifo_din   <= "11" & word3_r;
                  state         <= SEND_WORD4;
               when SEND_WORD4 =>
                  qt_fifo_din   <= hdr_last & word4_r;
                  -- if last_hit = '1' or run = '0' then
                  --    state      <= IDLE;
                  -- else 
                  --    state      <= SEND_WORD1;
                  -- end if;
                  i_busy <= '0';
                  word1_r <= word1;
                  word2_r <= word2;
                  word3_r <= word3;
                  word4_r <= word4;
                  state <= IDLE;

               when SEND_NULL =>
                  qt_wr_en      <= '1';
                  qt_fifo_din   <= "00" & x"FFFF";
                  state         <= IDLE;

            end case;
         end if;
      end if;

   end process SEND_DATA_PROC;

   busy <= i_busy or fifo_ren;

   ------------------------------------------------
   -- count how many times qt fifo gets full
   ------------------------------------------------
   process(clk)
   begin
      if rising_edge(clk) then
         i_qt_fifo_full_r <= i_qt_fifo_full;
         if i_qt_fifo_full = '1' and i_qt_fifo_full_r = '0' then
            i_qt_fifo_err_cnt <= i_qt_fifo_err_cnt + 1;
         end if;
      end if;
   end process;
   fifo_err_cnt <= i_qt_fifo_err_cnt;
   ------------------------------------------------

end beh;