MeasurePeds.vhd

-- Module Name:    MeasurePeds - Behavioral
-- Create Date:    09/29/2019
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
use IEEE.STD_LOGIC_MISC.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
Library work;
use work.klm_scint_pkg.all;



entity MeasurePeds is
    generic (
        LAST_WINDOW_ADDRESS    : std_logic_vector(8 downto 0) := "111111111";
        N_BITS_AVG_g           : integer;
        ANALOG_STORE_TIME      : std_logic_vector(8 downto 0) := "000001000" -- in 32ns (1 win) increments

    );
    Port (
        clk                  : in  STD_logic;
        ena                  : in  std_logic := '0';
        busy                 : out std_logic := '0';

        force_trig           : out std_logic := '0';
        trig_win             : out std_logic_vector(8 downto 0) := (others=>'0');
        prime_fifos          : out std_logic := '0';
        summing_ena          : out std_logic := '0';

        cur_win              : in std_logic_vector(8 downto 0);
        either_bus_busy  : in std_logic := '0';
        avg_peds_ena         : out std_logic := '0';
        avg_peds_busy        : in std_logic_vector(1 downto 0) := (others=>'0');
        dig_busy             : in std_logic
        -- bus_mask             : out std_logic_vector(13 downto 0)

    );
end MeasurePeds;

architecture Behavioral of MeasurePeds is


    type MeasurePeds_sm is (
        IDLE,
        WINDOW_LOOP,
        N_AVG_LOOP,
        WAIT_WIN,
        WAIT_DIG,
        WAIT_SHIFT,
        WAIT_FINISH_BEFORE_AVERAGING,
        WAIT_AVG_AND_WRITE_PEDS
    );
    signal ped_meas_state : MeasurePeds_sm := IDLE;

    signal ena_i : std_logic_vector(1 downto 0) := "00";

    constant T_wait_busy_to_come_up : integer := 31;
    -- constant LAST_WINDOW_ADDRESS : std_logic_vector(8 downto 0) := "111111111";
    -- constant LAST_WINDOW_ADDRESS : std_logic_vector(8 downto 0) := "000000011";

begin

    process (clk, ena)
    begin
        if rising_edge(clk) then
            ena_i(0) <= ena;
        end if;
    end process;


    process(clk, ena_i, either_bus_busy, avg_peds_busy, dig_busy)
        variable count          : integer range 0 to T_wait_busy_to_come_up := 0;
        -- variable count16bit     : std_logic_vector(16 downto 0);   
        variable N_avg_counter  : integer range 0 to 2**(1 + N_BITS_AVG_g) := 0;
        variable trig_win_i     : std_logic_vector(8 downto 0) := (others=>'0');
    begin
        if (rising_edge(clk)) then

            ena_i(1) <= ena_i(0);
            trig_win <= trig_win_i;

            case ped_meas_state is

                When IDLE =>
                    -- bus_mask <= (others=>'0');
                    if (ena_i = "01") then
                        busy <= '1';
                        trig_win_i := (others=>'0');
                        N_avg_counter := 0;
                        -- force_trig <= '1';
                        summing_ena <= '1';
                        prime_fifos <= '1'; -- prime all wave and ped fifos with 32 null vectors
                        ped_meas_state <= N_AVG_LOOP;
                    else
                        busy <= '0';
                        ped_meas_state <= IDLE;
                    end if;


                When WINDOW_LOOP =>
                    if trig_win_i /= LAST_WINDOW_ADDRESS then
                        trig_win_i := trig_win_i + "000000001";
                        summing_ena <= '1';
                        prime_fifos <= '1'; -- prime all wave and ped fifos with 32 null vectors
                        ped_meas_state <= N_AVG_LOOP;
                    else
                        ped_meas_state <= IDLE;
                    end if;


                When N_AVG_LOOP =>
                    prime_fifos <= '0';
                    if N_avg_counter < 2**N_BITS_AVG_g then
                        N_avg_counter := N_avg_counter + 1;
                        ped_meas_state <= WAIT_WIN;
                    else
                        N_avg_counter := 0;
                        count := 0;
                        ped_meas_state <= WAIT_FINISH_BEFORE_AVERAGING;
                    end if;
                
                
                When WAIT_WIN =>
                    if (cur_win - trig_win_i) = ANALOG_STORE_TIME then
                        force_trig <= '1';
                        -- bus_mask <= "10" & trig_win_i & "001"; -- mask(10) | win start | num windows -- wired to SamplingLgc
                        ped_meas_state <= WAIT_DIG;
                    else
                        ped_meas_state <= WAIT_WIN;
                    end if;


                When WAIT_DIG =>
                    force_trig <= '0';
                    -- bus_mask <= (others=>'0');
                    if dig_busy = '1' or count < T_wait_busy_to_come_up then
                        count := count + 1;
                        ped_meas_state <= WAIT_DIG;
                    else
                        count := 0;
                        -- count16bit := (others=>'0');
                        -- bus_mask <= "11" & trig_win_i & "001"; -- unmask(11) | win start | num windows -- now sampling will continue while we shift out data
                        ped_meas_state <= WAIT_SHIFT;
                    end if;
                    
                        
                When WAIT_SHIFT =>
                    -- bus_mask <= (others=>'0');
                    if either_bus_busy ='1' or count < T_wait_busy_to_come_up then
                    -- if count16bit(16) /= '1' then -- can maybe use cur_win from SamplingLgc_i in conjunction with above line instead of larger counter
                        -- count16bit := count16bit + '1';
                        count := count + 1;
                        ped_meas_state <= WAIT_SHIFT;
                    else
                        -- count16bit := (others=>'0');
                        count := 0;
                        ped_meas_state <= N_AVG_LOOP;
                    end if;


                When WAIT_FINISH_BEFORE_AVERAGING =>
                    if count < T_wait_busy_to_come_up then
                        count := count + 1;
                        ped_meas_state <= WAIT_FINISH_BEFORE_AVERAGING;
                    else
                        count := 0;
                        summing_ena <= '0';
                        avg_peds_ena <= '1';
                        ped_meas_state <= WAIT_AVG_AND_WRITE_PEDS;
                    end if;


                When WAIT_AVG_AND_WRITE_PEDS =>
                    avg_peds_ena <= '0';
                    if or_reduce(avg_peds_busy) = '1' or count < T_wait_busy_to_come_up then
                        count := count + 1;
                        ped_meas_state <= WAIT_AVG_AND_WRITE_PEDS;
                    else
                        count := 0;
                        ped_meas_state <= WINDOW_LOOP;
                    end if;



            end case;
        end if;
    end process;





end Behavioral;