SamplingLgc.vhd

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
library unisim;
use unisim.vcomponents.all;
library work;
use work.klm_scint_pkg.all;
--
-- Deficiencies: 
-- 1) generating SSTin using clock-counter probably not ideal. Should consider
--    using a divided clock from the pll_base.
--
-------------------------------------------------------------------------------


entity SamplingLgc is
    port (
        clk              : in  std_logic;  --expect input clock to be 8xSST = 62.5 MHz (now it is 127 MHz)
        reset            : in  std_logic := '0';  -- reset chip counters, it will reset the main counter and tells the TX chip to do so

        ana_wr_ena_mask  : in TARGETX_analong_wr_ena_mask_t; -- ena & sel & win_start(8:0) & N_win(2:0)

        cur_win          : out std_logic_vector(8 downto 0) := (others=>'0'); --COL & ROW write address- we just need this to keep track of the last sample taken
        BUSA_WR_ADDRCLR  : out std_logic := '0';  -- write address clear -- when asserted, it will reset the row and col on the TX chip
        BUSB_WR_ADDRCLR  : out std_logic := '0';  -- write address clear -- when asserted, it will reset the row and col on the TX chip
        WR1_ENA          : out std_logic_vector(9 downto 0) := (others=>'1');  -- Enable Write 1 procedure
        WR2_ENA          : out std_logic_vector(9 downto 0) := (others=>'1');  -- Enable Write 2 procedure

        SSTIN_N          : out std_logic_vector(9 downto 0) := (others=>'0'); --SCA control signals
        SSTIN_p          : out std_logic_vector(9 downto 0) := (others=>'1') --SCA control signals
    );
end SamplingLgc;

architecture Behavioral of SamplingLgc is


    --state machine drives SAMPLING logic signals directly
    type state_type is (
        RESETTING,
        SAMPLING
    );
    signal analog_store_state : state_type := RESETTING;

    -- current write address
    signal cur_win_i       : UNSIGNED(8 downto 0) := "000000000";

    -- wires to TargetX
    signal SSTIN_i         : std_logic := '0'; --SCA control signals
    signal wr_addrclr_i    : std_logic := '0'; --Clear Write Address Counter
    -- signal wr_ena          : std_logic := '1'; --Enable Write procedure
    signal wr_ena : std_logic_vector(9 downto 0) := (others => '1');

    signal clk_cntr : std_logic_vector(2 downto 0) := (others=>'0');

    signal wr_ena_mask : std_logic_vector(511 downto 0) := (others=>'1');

    signal i_reset : std_logic := '0';


--------------------------------------------------------------------------------

begin

    process(clk, cur_win_i)
    begin
        if rising_edge(clk) then
            cur_win <= std_logic_vector(cur_win_i(8 downto 0)); --output only row + colum sections
        end if;
    end process;

    SamplingMask : entity work.SamplingMask
    port map (
        clk         => clk,
        rst         => i_reset,
        ena         => ana_wr_ena_mask.ena,
        new_bit     => ana_wr_ena_mask.mask_bit,
        win_start   => ana_wr_ena_mask.win_start,
        N_win       => ana_wr_ena_mask.n_win,
        wr_ena_mask => wr_ena_mask
    );


    -- latch reset to local domain
    process(clk, reset)
    begin
        if rising_edge(clk) then
            i_reset <= reset;
        end if;
    end process;


    -- Generate SSTIN
    SSTIN_PROC : process(clk, clk_cntr)
    begin
        if rising_edge(clk) then
            clk_cntr <= clk_cntr + "001";
            SSTIN_i <= clk_cntr(2); -- clk is 127 MHz now, SSTIN period is clk*4
        end if;
    end process SSTIN_PROC;
    -- SSTIN <= SSTIN_i;


    -- Assert mask on write-enable pins
    process(clk, wr_ena_mask, cur_win_i)
    begin
        if (rising_edge(clk)) then
            for i in 0 to 9 loop
                wr_ena(i) <= wr_ena_mask(to_integer(cur_win_i));
            end loop;
        end if;
    end process;
    WR1_ENA <= wr_ena;
    WR2_ENA <= wr_ena;


    -- Main Sampling FSM
    process(clk, cur_win_i, i_reset, SSTIN_i, clk_cntr)
    begin
        if (rising_edge(clk)) then
            if (i_reset='1') then
                 wr_addrclr_i <= '1';
                 cur_win_i <= (others=>'0');
                 analog_store_state <= RESETTING; -- do a one time thing to bring the counter up at the correct phase
            else
                case analog_store_state is

                    when RESETTING =>
                        cur_win_i <= (others=>'0');
                        -- if ( clk_cntr(1 downto 0) = cfg_i(1 downto 0) ) then
                        if (SSTIN_i = '0' and clk_cntr(2) = '1') then -- rising edge of sstin
                            wr_addrclr_i <= '0';
                            analog_store_state <= SAMPLING;
                        else
                            --keep wr_addrclr high for afew clock cycles.
                            wr_addrclr_i <= '1';
                            analog_store_state <= RESETTING;
                        end if;

                    when SAMPLING =>
                        wr_addrclr_i <= '0';
                        -- if (clk_cntr(1 downto 0) = "01" or clk_cntr(1 downto 0) = "11") then
                        if ( SSTIN_i = '0' and clk_cntr(2) = '1') or (SSTIN_i = '1' and clk_cntr(2) = '0') then -- rising or falling
                            cur_win_i <= cur_win_i + 1;
                        else
                            cur_win_i <= cur_win_i;
                        end if;
                        analog_store_state <= SAMPLING;

                    when others =>
                        cur_win_i <= (others => '-');
                        analog_store_state <= SAMPLING;

                end case;
            end if;
        end if;
    end process;
    BUSA_WR_ADDRCLR <= wr_addrclr_i;
    BUSB_WR_ADDRCLR <= wr_addrclr_i;

    GEN_SSTIN : for i in 0 to 9 generate
        obuf_ds_sstin_i : OBUFDS port map ( i => SSTIN_i, o => SSTIN_P(i), ob => SSTIN_N(i));
    end generate;

end Behavioral;