Belle II KLM Scint Firmware  1
Behavioral Architecture Reference

Processes

PROCESS_32  ( clk , cur_win_i )
PROCESS_33  ( clk , reset )
SSTIN_PROC  ( clk , clk_cntr )
PROCESS_34  ( clk , wr_ena_mask , cur_win_i )
PROCESS_35  ( clk , cur_win_i , i_reset , SSTIN_i , clk_cntr )

Types

state_type ( RESETTING , SAMPLING )

Signals

analog_store_state  state_type := RESETTING
cur_win_i  UNSIGNED ( 8 downto 0 ) := " 000000000 "
SSTIN_i  std_logic := ' 0 '
wr_addrclr_i  std_logic := ' 0 '
wr_ena  std_logic_vector ( 9 downto 0 ) := ( others = > ' 1 ' )
clk_cntr  std_logic_vector ( 2 downto 0 ) := ( others = > ' 0 ' )
wr_ena_mask  std_logic_vector ( 511 downto 0 ) := ( others = > ' 1 ' )
i_reset  std_logic := ' 0 '

Instantiations

samplingmask  SamplingMask <Entity SamplingMask>
obuf_ds_sstin_i  obufds

Detailed Description

Definition at line 51 of file SamplingLgc.vhd.


The documentation for this class was generated from the following file: