Behavioral Architecture Reference

Processes
PROCESS_7	( clk , b2tt_ctime_i )
startup_latch_proc	( clk , b2tt_utime , b2tt_b2clkup , b2tt_b2ttup , b2tt_b2ttup_r , b2tt_b2ttup_2r , ScrodControl.B2ttDbg )
b2tt_dbg2reg_proc	( clk )
rst_conc_intfc_on_startup	( clk , b2tt_runreset )
stat_reg_ppln	( clk , klm_status_regs )

Signals
b2tt_b2clkup_r	std_logic
	startup_latch_proc:
b2tt_b2ttup_r	std_logic
b2tt_b2ttup_2r	std_logic
b2tt_regdbg	std_logic_vector ( 7 downto 0 ) := ( others = > ' 0 ' )
ScrodStatus	KlmScrodStatusType := KlmScrodStatusType0
	b2tt_dbg2reg_proc:
klmifc_reset	std_logic := ' 0 '
	trgon_sw_4scaler_mode:
klmifc_reset_done	std_logic := ' 0 '
klm_status_regs_r	stat_reg_type
	stat_reg_ppln:
clk	std_logic := ' 0 '
	asic_and_channel_multiplexer_for_mppc_current_measurement: b2tt_i (b2tt):
clkinv	std_logic := ' 0 '
clk2x	std_logic := ' 0 '
b2tt_b2clkup	std_logic
b2tt_b2ttup	std_logic
b2tt_trgout	std_logic
b2tt_sigbit2	std_logic_vector ( 1 downto 0 )
b2tt_trgtag	std_logic_vector ( 31 downto 0 )
b2tt_utime	std_logic_vector ( B2TT_NBITTIM- 1 downto 0 )
b2tt_ctime	std_logic_vector ( 26 downto 0 ) := ( others = > ' 0 ' )
b2tt_divclk1	std_logic_vector ( 1 downto 0 )
b2tt_divclk2	std_logic_vector ( 1 downto 0 )
b2tt_runreset	std_logic := ' 1 '
b2tt_feereset	std_logic := ' 1 '
b2tt_gtpreset	std_logic := ' 1 '
b2tt_b2lreset	std_logic := ' 1 '
b2tt_b2ttver	std_logic_vector ( 15 downto 0 )
b2tt_fifordy	std_logic := ' 0 '
b2tt_fifodata	std_logic_vector ( 95 downto 0 ) := ( others = > ' 0 ' )
b2tt_exprun	std_logic_vector ( 31 downto 0 )
b2tt_frame	std_logic
b2tt_frame9	std_logic
b2tt_dbglink	std_logic_vector ( 95 downto 0 ) := ( others = > ' 0 ' )
b2tt_b2linkwe	std_logic := ' 0 '
	KLM_Interface_i (klm_intfc):
b2tt_fifonext	std_logic := ' 0 '
rcl_src_rdy_n	std_logic
rcl_data	std_logic_vector ( 15 downto 0 )
aurora_stat	Aurora_Status_t
i_qt_fifo_rd_en	std_logic
i_exttb	tb_vec_type
stat_tx_in_progress	std_logic
ScrodConfig	KlmScrodConfigType := KlmScrodConfigZero
	Register_Control_i (KLMScrodRegCtrl):
ScrodControl	KlmScrodControlType
klm_status_regs	stat_reg_type
i_qt_fifo_d	std_logic_vector ( 17 downto 0 )
	Readout_Control_i (KLMReadoutCtrl):
i_qt_fifo_empty	std_logic
i_qt_fifo_evt_rdy	std_logic
asic_sin	std_logic := ' 0 '
	targetx_dac_control_i (targetx_dac_control):
asic_pclk	std_logic := ' 0 '
asic_sclk	std_logic := ' 0 '
SCK_DAC	std_logic := ' 0 '
	mppc_hv_dac_wrapper_i (mppc_dacs_wrapper_dac088s085):
DIN_DAC	std_logic := ' 0 '
wilk_clk	std_logic_vector ( 9 downto 0 ) := ( others = > ' 0 ' )
	clock_frequency_doubling
b2tt_ctime_i	std_logic_vector ( 26 downto 0 ) := ( others = > ' 0 ' )
	sim_true_false:
b2tt_trig	std_logic
i_force_trig	std_logic

Instantiations
b2tt_i	b2tt <Entity b2tt>
klm_interface_i	klm_intfc <Entity klm_intfc>
register_control_i	KLMScrodRegCtrl <Entity KLMScrodRegCtrl>
readout_control_i	KLMReadoutCtrl <Entity KLMReadoutCtrl>
targetx_dac_control_i	TARGETX_DAC_CONTROL <Entity TARGETX_DAC_CONTROL>
mppc_hv_dac_wrapper_i	mppc_dacs_wrapper_dac088s085 <Entity mppc_dacs_wrapper_dac088s085>
clock_frequency_doubling	oddr2
differential_output_buffer	obufds

Detailed Description

Definition at line 322 of file klm_scint.vhd.

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The documentation for this class was generated from the following file:

• klm_scint/source/klm_scint.vhd