TARGETX_DAC_CONTROL Entity Reference

Inheritance diagram for TARGETX_DAC_CONTROL:

Entities
Behavioral	architecture

Libraries
IEEE

Use Clauses
STD_LOGIC_1164
NUMERIC_STD

Generics
REGISTER_WIDTH	integer := 19

Ports
CLK	in STD_LOGIC
LOAD_PERIOD	in STD_LOGIC_VECTOR ( 3 downto 0 )
LATCH_PERIOD	in STD_LOGIC_VECTOR ( 3 downto 0 )
UPDATE	in STD_LOGIC
REG_DATA	in STD_LOGIC_VECTOR ( 18 downto 0 )
busy	out std_logic
SIN	out STD_LOGIC
SCLK	out STD_LOGIC
PCLK	out STD_LOGIC

Detailed Description

Definition at line 27 of file tx_dac_control.vhd.

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The documentation for this class was generated from the following file:

• peripherals/tx_dac_control.vhd