klm_scint Entity Reference

Inheritance diagram for klm_scint:

Entities
Behavioral	architecture

Libraries
ieee
unisim
unimacro

Use Clauses
std_logic_1164
numeric_std
std_logic_unsigned
std_logic_misc
vcomponents
all
tdc_pkg
time_order_pkg
conc_intfc_pkg	Package <conc_intfc_pkg>
klm_scrod_pkg	Package <klm_scrod_pkg>
klm_scint_pkg	Package <klm_scint_pkg>

Generics
NUM_GTS	integer := 1
B2TT_SIM_SPEEDUP	std_logic := ' 0 '
IS_SIM	std_logic := ' 0 '
SLOW_CTRL_BUFF	integer := 7
VERSION	std_logic_vector ( 15 downto 0 ) := X " FE00 "

Ports
force_trig	in std_logic
TTDCLKP	in std_logic
	FTSW.
TTDCLKN	in std_logic
TTDACKP	out std_logic
TTDACKN	out std_logic
TTDTRGP	in std_logic
TTDTRGN	in std_logic
TTDRSVP	out std_logic
TTDRSVN	out std_logic
mgttxfault	in std_logic_vector ( 1 to NUM_GTS )
	SFP.
mgtmod0	in std_logic_vector ( 1 to NUM_GTS )
mgtlos	in std_logic_vector ( 1 to NUM_GTS )
mgttxdis	out std_logic_vector ( 1 to NUM_GTS )
mgtmod2	out std_logic_vector ( 1 to NUM_GTS )
mgtmod1	out std_logic_vector ( 1 to NUM_GTS )
mgtrxp	in std_logic
mgtrxn	in std_logic
mgttxp	out std_logic
mgttxn	out std_logic
mgtclk0p	in std_logic
mgtclk0n	in std_logic
mgtclk1p	in std_logic
mgtclk1n	in std_logic
BUSA_WR_ADDRCLR	out std_logic
	MB Specific Signals BUS A Specific Signals.
BUSA_RD_ENA	out std_logic
BUSA_RD_ROWSEL	out std_logic_vector ( 2 downto 0 )
BUSA_RD_COLSEL	out std_logic_vector ( 5 downto 0 )
BUSA_CLR	out std_logic
BUSA_RAMP	out std_logic
BUSA_SAMPLESEL	out std_logic_vector ( 4 downto 0 )
BUSA_SR_CLEAR	out std_logic
BUSA_SR_SEL	out std_logic
BUSA_DO	in std_logic_vector ( 14 downto 0 )
BUSB_WR_ADDRCLR	out std_logic
	Bus B Specific Signals.
BUSB_RD_ENA	out std_logic
BUSB_RD_ROWSEL	out std_logic_vector ( 2 downto 0 )
BUSB_RD_COLSEL	out std_logic_vector ( 5 downto 0 )
BUSB_CLR	out std_logic
BUSB_RAMP	out std_logic
BUSB_SAMPLESEL	out std_logic_vector ( 4 downto 0 )
BUSB_SR_CLEAR	out std_logic
BUSB_SR_SEL	out std_logic
BUSB_DO	in std_logic_vector ( 14 downto 0 )
SIN	out std_logic_vector ( 9 downto 0 )
	ASIC DAC Update Signals.
PCLK	out std_logic_vector ( 9 downto 0 )
SHOUT	in std_logic_vector ( 9 downto 0 )
SCLK	out std_logic_vector ( 9 downto 0 )
WL_CLK_N	out std_logic_vector ( 9 downto 0 )
	Digitization and sampling signals.
WL_CLK_P	out std_logic_vector ( 9 downto 0 )
WR1_ENA	out std_logic_vector ( 9 downto 0 )
WR2_ENA	out std_logic_vector ( 9 downto 0 )
SSTIN_N	out std_logic_vector ( 9 downto 0 )
SSTIN_P	out std_logic_vector ( 9 downto 0 )
SR_CLOCK	out std_logic_vector ( 9 downto 0 )
	Serial Readout Signals.
SAMPLESEL_ANY	out std_logic_vector ( 9 downto 0 )
BUSA_SCK_DAC	out std_logic
	MPPC HV DAC.
BUSA_DIN_DAC	out std_logic
BUSB_SCK_DAC	out std_logic
BUSB_DIN_DAC	out std_logic
TARGET_TB	in tb_vec_type
	TRIGGER SIGNALS.
TDC_CS_DAC	out std_logic_vector ( 9 downto 0 )
TDC_AMUX_S	out std_logic_vector ( 3 downto 0 )
	Target Daugher Card Channel Select - Fanned out to 10 MUXs.
TOP_AMUX_S	out std_logic_vector ( 3 downto 0 )
RAM_ADDR	out std_logic_vector ( 21 downto 0 )
	PED SRAM.
RAM_IO	inout std_logic_vector ( 7 downto 0 )
RAM_CEb	out std_logic
RAM_CE	out std_logic
RAM_OEb	out std_logic
RAM_WEb	out std_logic

Detailed Description

Operation of klm_scint module:

This is the top-level module (all of the FPGA's physical pins are the ports of this module). Within this module, the three largest module instantiations are b2tt, klm_intfc, and KLMReadoutCtrl. B2tt, as the acronym suggets, handles trigger and timing for BelleII (RJ45). Klm_intfc sends and receives data to and from the Data Concentrator, including configuration/status registers and DAQ packets (Aurora SFP). KLMReadoutCtrl processes primitive triggers and waveforms from all 150 TARGETX channels, and it also manages analog sampling strobes, digitization, & SRAM access for pedestal subtraction

Definition at line 179 of file klm_scint.vhd.

Member Data Documentation

TOP_AMUX_S

TOP_AMUX_S out std_logic_vector ( 3 downto 0 )

Port

Top-level mux - 0-9: ASIC, 11-15 for debug. 10:testpoint, 11:ASIC5DAC15_mon, 12: 5/2 V Ref. 13: 3.3 V Ref, 14: 2.5 V Ref, 15: 4.75/2 V Ref

Definition at line 302 of file klm_scint.vhd.

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The documentation for this class was generated from the following file:

• klm_scint/source/klm_scint.vhd