Belle II KLM Scint Firmware  1
b2tt.vhd
1 -- ---------------------------------------------------------------------
2 --
3 --- b2tt.vhd --- Belle II TT-link receiver top
4 --
5 -- This firmware is a reference design for a frontend board
6 -- which is connected to ft2u firmware
7 --
8 -- (Note: there are still missing features,
9 -- marked with TBI = to be implemented.)
10 --
11 -- Mikihiko Nakao, KEK IPNS
12 --
13 --- revisions
14 -- 20130530 0.01 first version
15 -- (there are many intermediate versions between 0.01 and 0.02)
16 -- 20130926 0.02 revised (revo/revo9, b2ltag in ack packet)
17 -- 20131002 0.03 revised (exprun, b2tt_ddr.vhd)
18 -- 20131013 0.04 merging v5,v6,s6 versions
19 -- 20131028 0.05 fixing b2tt_ddr
20 -- 20131101 0.06 no more std_logic_arith
21 -- 20131110 0.07 96-bit fifodata for final(?) header format
22 -- 20131118 0.08 all open ports are connected to dummy signals
23 -- 20131119 0.09 S6 iodelay2 fix
24 -- 20131121 0.10 tested with S6/V5/V6, more iodelay monitor and control
25 -- 20131127 0.11 duplicated header fix (bug in b2tt_fifo)
26 -- 20131218 0.12 entagerr added
27 -- 20140102 0.13 fix for one-pulse err signal, tagerr check ini.values
28 -- 20140406 0.14 ttup error study
29 -- 20140409 0.15 crc8 trial
30 -- 20140607 0.16 b2tt version output
31 -- 20140611 0.17 revised dbg for chipscope of KLM data concentrator
32 -- 20140614 0.18 port 0.17 changes to v5 and s6
33 -- 20140618 0.19 iserdes version for v6
34 -- 20140704 0.20 interface adjustment for v5 and s6
35 -- 20140708 0.21 iserdes version for v6 tuning
36 -- 20140710 0.22 crc8 for rx, ila revised, signals for scan mode
37 -- 20140710 0.23 no sigslip version (scan test, only for v6)
38 -- 20140710 0.24 delay scan (calc test, only for v6)
39 -- 20140710 0.25 delay scan and set (only for v6)
40 -- 20140715 0.26 improved error handling
41 -- 20140718 0.27 b2ttup and b2lup should be current status
42 -- 20140729 0.28 new b2tt_symbols for ft2u059
43 -- 20140808 0.29 b2tt_payload separated from b2tt_encode
44 -- 20140827 0.30 one frame long runreset, busyup at runreset fix
45 -- 20140902 0.31 sim_speedup, optional external clock source
46 -- 20141002 0.32 gtpreset when clk is lost and recovered
47 -- 20150105 0.33 no more raw ddr signal out, rawclk after bufg
48 -- 20150112 0.34 jtag handling, trgmask, cleanup unused signals
49 -- 20150112 0.35 timerr fix
50 -- 20150227 0.36 merging trgmask fixes
51 -- 20150310 0.37 clraddr, stareset
52 -- 20150428 0.38 b2tt encode fix, decode clraddr
53 -- 20150525 0.39 b2tt decode to no tagerr when mask is cleared
54 -- 20150528 0.40 DIVCLK fix
55 -- 20150630 0.41 254MHz clock input option for DHH with recovered clock
56 -- 20150718 0.42 b2tt decode fix mix up is fixed
57 -- 20150723 0.43 changes: spartan-6 invclock, cnt_trig for timing constraint
58 -- 20160315 0.44 b2tt_decode trgmask
59 -- 20160316 0.45 SEU mitigation bits rearranged
60 -- 20160407 0.46 trgtag + 1 before filling fifo, trgmask fix
61 -- 20160627 0.47 trgtag update timing, no more trgtag + 1 before fifo
62 -- 20160628 0.48 fix tagerr in 0.47
63 -- 20170403 0.49 major payload rearrangement
64 -- 20170406 0.50 further rearrangement for ft3o
65 -- 20170713 0.51 frame, revo, injv, rstmask, usrreg
66 -- 20170724 0.52 error code cleanup, semreset
67 --
68 -- ---------------------------------------------------------------------
69 
70 --- b2tt: libraries
71 library ieee;
72 use ieee.std_logic_1164.all;
73 use ieee.std_logic_unsigned.all;
74 use ieee.numeric_std.all;
75 library work;
76 use work.b2tt_symbols.all;
77 
78 --- b2tt: entity
79 entity b2tt is
80  --- generic
81  generic (
82  SUBSYSTEM : std_logic_vector (3 downto 0) := TTFEE_UNDEF;
83  FWTYPE : integer := 0;
84  VERSION : integer := 0;
85 
86  B2TT_VER : integer := 52;
87  PROTOCOL : integer := 30;
88  COMPAT : integer := 29; -- for transition to new protocol
89  DEFADDR : std_logic_vector (19 downto 0) := x"00000";
90  FLIPCLK : std_logic := '0'; -- no more used
91  FLIPTRG : std_logic := '0';
92  FLIPACK : std_logic := '0';
93  USEFIFO : std_logic := '1';
94  CLKDIV1 : integer range 1 to 72 := 3;
95  CLKDIV2 : integer range 1 to 72 := 4;
96  USEPLL : std_logic := '0';
97  USEICTRL : std_logic := '1';
98  NBITTIM : integer range 1 to 32 := 32;
99  NBITTAG : integer range 4 to 32 := 32;
100  --NBITID : integer range 4 to 32 := 16; fixed to 16 bit
101  B2LRATE : integer := 4; -- 127 Mbyte / s
102  USEEXTCLK : std_logic := '0';
103  USE254IN : std_logic := '0'; -- 254 MHz clock in for DHH
104  SIM_SPEEDUP : std_logic := '0' );
105  --- port
106  port (
107  --- b2tt version
108  b2ttver : out std_logic_vector (15 downto 0);
109 
110  --- RJ-45
111  clkp : in std_logic;
112  clkn : in std_logic;
113  trgp : in std_logic;
114  trgn : in std_logic;
115  rsvp : out std_logic;
116  rsvn : out std_logic;
117  ackp : out std_logic;
118  ackn : out std_logic;
119 
120  --- alternative external clock source
121  extclk : in std_logic;
122  extclkinv : in std_logic;
123  extclkdbl : in std_logic;
124  extdblinv : in std_logic;
125  extclklck : in std_logic;
126 
127  --- board id
128  id : in std_logic_vector (15 downto 0);
129 
130  -- user status register (for debug)
131  usrreg : out std_logic_vector (7 downto 0);
132  usrdat : in std_logic_vector (15 downto 0);
133 
134  --- link status
135  b2clkup : out std_logic;
136  b2ttup : out std_logic;
137 
138  --- system clock and time
139  sysclk : out std_logic;
140  sysclkinv : out std_logic; --#CK, bring out for wilk_clk
141  rawclk : out std_logic;
142  dblclk : out std_logic;
143  hlfclk : out std_logic;
144  utime : out std_logic_vector (NBITTIM-1 downto 0);
145  ctime : out std_logic_vector (26 downto 0);
146 
147  --- divided clock
148  divclk1 : out std_logic_vector (1 downto 0);
149  divclk2 : out std_logic_vector (1 downto 0);
150 
151  --- exp- / run-number
152  exprun : out std_logic_vector (31 downto 0);
153  running : out std_logic;
154 
155  --- run reset
156  runreset : out std_logic;
157  feereset : out std_logic;
158  b2lreset : out std_logic;
159  gtpreset : out std_logic;
160  rstmask : out std_logic; -- for runreset
161 
162  --- trigger
163  trgout : out std_logic;
164  trgtyp : out std_logic_vector (3 downto 0);
165  trgtag : out std_logic_vector (31 downto 0);
166  trgmask : out std_logic;
167 
168  --- revolution
169  frame : out std_logic;
170  --revo3 : out std_logic;
171  frame9 : out std_logic;
172  revoloc : out std_logic_vector (10 downto 0);
173  revosig : out std_logic;
174  abortgap : out std_logic;
175  injveto : out std_logic;
176  injkick : out std_logic;
177  injvpos : out std_logic_vector (10 downto 0);
178  injvpre : out std_logic_vector (10 downto 0);
179  injvlen : out std_logic_vector (10 downto 0);
180  injvfull : out std_logic_vector (9 downto 0);
181  injvgate : out std_logic_vector (9 downto 0);
182 
183  --- busy and status return
184  busysrc : in std_logic_vector (7 downto 0); -- to suspend the trigger
185  feeerr : in std_logic_vector (7 downto 0); -- to stop the run
186 
187  --- Belle2link status
188  b2plllk : in std_logic;
189  b2linkup : in std_logic;
190  b2linkwe : in std_logic;
191  b2lclk : in std_logic;
192 
193  --- SEM status (virtex5_seu_controller or SEU mitigation ipcore)
194  semscan : in std_logic; -- end_of_scan / watchdog (=> 1 bit)
195  semdet : in std_logic; -- seu_detect / corrected (=> 2 bit counter)
196  semmbe : in std_logic; -- mbe/uncorrectable
197  semcrc : in std_logic; -- crc_error (virtex5 only) (=> combined)
198 
199  --- data for Belle2link header
200  fifordy : out std_logic;
201  fifodata : out std_logic_vector (95 downto 0);
202  fifonext : in std_logic;
203 
204  --- b2tt-link status
205  regdbg : in std_logic_vector (7 downto 0);
206  octet : out std_logic_vector (7 downto 0); -- decode
207  isk : out std_logic; -- decode
208  cntbit2 : out std_logic_vector (2 downto 0); -- decode
209  sigbit2 : out std_logic_vector (1 downto 0); -- decode
210  dbglink : out std_logic_vector (95 downto 0);
211  dbgerr : out std_logic_vector (95 downto 0) );
212 
213 end b2tt;
214 --- b2tt: architecture
215 architecture implementation of b2tt is
216 
217  signal clk_i : std_logic := '0';
218  signal clk_inv : std_logic := '0';
219  signal clk_dbl : std_logic := '0';
220  signal clk_dblinv : std_logic := '0';
221  ------ sig_254s : std_logic := '0';
222 
223  signal regin : std_logic_vector (5 downto 0) := (others => '0');
224  signal reg_imanual : std_logic := '0';
225  signal clr_idelay : std_logic := '0';
226  signal set_idelay : std_logic := '0';
227  signal sig_caldelay : std_logic := '0';
228 
229  signal sta_dcm : std_logic := '0';
230  signal buf_myaddr : std_logic_vector (19 downto 0) := DEFADDR;
231  signal sta_ictrl : std_logic_vector (1 downto 0) := "11";
232 
233  signal sta_utime : std_logic_vector (31 downto 0) := (others => '0');
234  signal sta_ctime : std_logic_vector (26 downto 0) := (others => '0');
235  signal sta_timerr : std_logic := '0';
236  signal sig_runreset : std_logic := '0';
237  signal sig_errreset : std_logic := '0';
238  signal sig_trig : std_logic := '0';
239  signal sta_trgtyp : std_logic_vector (3 downto 0) := (others => '0');
240  signal sta_trgtag : std_logic_vector (31 downto 0) := (others => '1');
241  signal sta_tagerr : std_logic := '0';
242  signal sta_trgmask : std_logic := '0';
243  signal sta_rstmask : std_logic := '0';
244 
245  signal sta_trgshort : std_logic := '0';
246  signal sta_octet : std_logic := '0';
247  signal sta_ttup : std_logic := '0';
248  signal cnt_linkrst : std_logic_vector (7 downto 0) := (others => '0');
249  signal sig_frame : std_logic := '0';
250  signal sig_frame3 : std_logic := '0';
251  signal sig_frame9 : std_logic := '0';
252  signal cnt_frameloc : std_logic_vector (10 downto 0) := (others => '0');
253  signal buf_revoloc : std_logic_vector (10 downto 0) := (others => '0');
254  signal buf_payload : std_logic_vector (76 downto 0) := (others => '0');
255  signal sig_payload : std_logic := '0';
256  signal sig_idle : std_logic := '0';
257 
258  signal cnt_packet : std_logic_vector (7 downto 0) := (others => '0');
259  signal cnt_idelay : std_logic_vector (6 downto 0) := (others => '0');
260  signal cnt_iwidth : std_logic_vector (5 downto 0) := (others => '0');
261  signal sta_iddr : std_logic_vector (1 downto 0) := (others => '0');
262  signal sta_rxerr : std_logic_vector (8 downto 0) := (others => '0');
263 
264  signal sta_fifoful : std_logic := '0';
265  signal sta_fifoemp : std_logic := '0'; -- unused
266  signal sta_fifoerr : std_logic := '0';
267  signal sta_fifordy : std_logic := '0';
268 
269  signal sig_trgdat : std_logic_vector (95 downto 0) := (others => '0');
270 
271  signal buf_rxisk : std_logic := '0';
272  signal buf_rxoctet : std_logic_vector (7 downto 0) := (others => '0');
273  signal buf_rxbit2 : std_logic_vector (1 downto 0) := (others => '0');
274  signal buf_rxcnt2 : std_logic_vector (2 downto 0) := (others => '0');
275  signal buf_rxcnto : std_logic_vector (4 downto 0) := (others => '0');
276  signal buf_rxcntd : std_logic_vector (3 downto 0) := (others => '0');
277 
278  signal cnt_ftag : std_logic_vector (15 downto 0) := (others => '0');
279  signal cnt_b2lwe : std_logic_vector (15 downto 0) := (others => '0');
280 
281  signal buf_txdata : std_logic_vector (111 downto 0) := (others => '0');
282  signal sig_txfill : std_logic;
283 
284  signal sta_bsyin : std_logic := '0';
285  signal sta_errin : std_logic := '0';
286 
287  -- unused signals defined for poor simulator
288  signal open_jtag : std_logic_vector (2 downto 0) := (others => '0');
289  signal open_jtagdbg : std_logic_vector (9 downto 0) := (others => '0');
290  signal open_clkfreq : std_logic_vector (23 downto 0) := (others => '0');
291  signal open_stat : std_logic_vector (1 downto 0) := (others => '0');
292  signal open_drd : std_logic_vector (95 downto 0) := (others => '0');
293  signal open_dbg : std_logic_vector (17 downto 0) := (others => '0');
294  signal open_bit10 : std_logic_vector (9 downto 0) := (others => '0');
295  signal open_clraddr : std_logic := '0';
296  signal open_bsyrst : std_logic := '0';
297  signal open_dismask : std_logic := '0';
298 
299  -- signals for debug and chipscope
300  signal buf_txcnt2 : std_logic_vector (2 downto 0) := (others => '0');
301  signal buf_txcnto : std_logic_vector (3 downto 0) := (others => '0');
302  signal buf_txisk : std_logic := '0';
303  signal buf_txoctet : std_logic_vector (7 downto 0) := (others => '0');
304  signal buf_txbit2 : std_logic_vector (1 downto 0) := (others => '0');
305  signal buf_txbsyup : std_logic := '0';
306  signal buf_txbsydn : std_logic := '0';
307 
308  signal sig_iddrdbg : std_logic_vector (9 downto 0) := (others => '0');
309  signal sig_crcdbg : std_logic_vector (8 downto 0) := (others => '0');
310 
311  signal sta_badver : std_logic := '0';
312 
313  signal seq_dcm : std_logic_vector (1 downto 0) := "11";
314  signal sig_clklost : std_logic := '0';
315  signal clk_raw : std_logic := '0';
316  signal sig_gtpreset : std_logic := '0';
317  signal sig_semreset : std_logic := '0';
318 
319  signal buf_regsel : std_logic_vector (4 downto 0) := (others => '0');
320  signal buf_usrreg : std_logic_vector (7 downto 0) := (others => '0');
321  signal buf_id : std_logic_vector (23 downto 0) := (others => '0');
322  signal buf_ver : std_logic_vector (23 downto 0) := (others => '0');
323 
324  signal buf_idly : std_logic_vector (23 downto 0) := (others => '0');
325 
326 --- b2tt: begin
327 begin
328  --- in
329  regin <= regdbg(5 downto 0);
330  reg_imanual <= regin(0);
331  set_idelay <= regin(2);
332  clr_idelay <= regin(3);
333  sig_caldelay <= regin(4);
334  buf_idly <= "000000" & cnt_iwidth & '0' & cnt_idelay & "00" & sta_iddr;
335 
336  --- map: b2tt_clk
337  gen_useextclk0: if USEEXTCLK = '0' generate
338  map_clk: entity work.b2tt_clk
339  generic map (
340  USEPLL => USEPLL,
341  USEICTRL => USEICTRL,
342  USE254IN => USE254IN )
343  port map (
344  clkp => clkp,
345  clkn => clkn,
346  reset => '0', -- (probably there's no way to reset)
347  rawclk => clk_raw, -- out
348  clock => clk_i, -- out
349  invclock => clk_inv, -- out
350  dblclock => clk_dbl, -- out
351  dblclockb => clk_dblinv, -- out
352  hlfclock => hlfclk,
353  locked => sta_dcm, -- out
354  stat => sta_ictrl ); -- out
355  end generate;
356  gen_useextclk1: if USEEXTCLK = '1' generate
357  clk_i <= extclk;
358  clk_inv <= extclkinv;
359  clk_dbl <= extclkdbl;
360  clk_dblinv <= extdblinv;
361  clk_raw <= extclk;
362  sta_dcm <= extclklck;
363  end generate;
364 
365  --- proc_clk_raw
366  proc_clk_raw: process (clk_raw)
367  begin
368  if rising_edge(clk_raw) then
369  seq_dcm <= seq_dcm(0) & sta_dcm;
370  sig_clklost <= seq_dcm(0) and (not seq_dcm(1));
371  end if;
372  end process;
373 
374  --- async signals
375  gtpreset <= sig_gtpreset or sig_clklost;
376 
377  sig_trgdat <= sta_fifoerr & sta_ctime(26 downto 0) & sta_trgtyp(3 downto 0) &
378  sta_trgtag(31 downto 0) &
379  sta_utime(31 downto 0);
380 
381  --- map: b2tt_fifo
382  map_fifo: entity work.b2tt_fifo
383  port map (
384  -- input
385  clock => clk_i,
386  enfifo => USEFIFO,
387  clr => sig_runreset,
388  wr => sig_trig,
389  din => sig_trgdat,
390  rd => fifonext,
391  ready => sta_fifordy,
392  dout => fifodata, -- out
393  drd => open_drd, -- out
394  err => sta_fifoerr, -- out
395  dbg => open_dbg, -- out
396  empty => sta_fifoemp, -- out
397  full => sta_fifoful ); -- out
398 
399  --- map: b2tt_revo
400  map_revo: entity work.b2tt_revo
401  port map (
402  clock => clk_i,
403  cntpacket => cnt_packet, -- 7:0
404  frameloc => cnt_frameloc, -- 10:0
405  sigpayload => sig_payload,
406  payload => buf_payload, -- 76:0
407  revoloc => buf_revoloc, -- out 10:0
408  revosig => revosig, -- out
409  abortgap => abortgap ); -- out
410 
411  --- map: b2tt_injv
412  map_injv: entity work.b2tt_injv
413  port map (
414  clock => clk_i,
415  cntpacket => cnt_packet, -- 7:0
416  frameloc => cnt_frameloc, -- 10:0
417  revoloc => buf_revoloc, -- 10:0
418  sigpayload => sig_payload,
419  payload => buf_payload, -- 76:0
420  injkick => injkick, -- out
421  injveto => injveto, -- out
422  injvpos => injvpos, -- out 10:0
423  injvpre => injvpre, -- out 10:0
424  injvlen => injvlen, -- out 10:0
425  injvfull => injvfull, -- out 9:0
426  injvgate => injvgate ); -- out 9:0
427 
428  --- map: b2tt_decode
429  map_decode: entity work.b2tt_decode
430  generic map (
431  PROTOCOL => PROTOCOL,
432  COMPAT => COMPAT,
433  FLIPTRG => FLIPTRG,
434  DEFADDR => DEFADDR,
435  CLKDIV1 => CLKDIV1,
436  CLKDIV2 => CLKDIV2,
437  SIM_SPEEDUP => SIM_SPEEDUP )
438  port map (
439  -- input
440  clock => clk_i,
441  invclock => clk_inv,
442  dblclock => clk_dbl,
443  dblclockb => clk_dblinv,
444  ckup => sta_dcm,
445  trgp => trgp,
446  trgn => trgn,
447 
448  -- system time
449  clkfreq => open_clkfreq, -- out
450  utime => sta_utime, -- out
451  ctime => sta_ctime, -- out
452  timerr => sta_timerr, -- out
453 
454  -- exp- / run-number
455  exprun => exprun, -- out
456  running => running, -- out
457  clraddr => open_clraddr, -- out
458  myaddr => buf_myaddr, -- out
459 
460  -- reset out
461  runreset => sig_runreset, -- out
462  errreset => sig_errreset, -- out
463  bsyreset => open_bsyrst, -- out
464  feereset => feereset, -- out
465  b2lreset => b2lreset, -- out
466  gtpreset => sig_gtpreset, -- out
467  semreset => sig_semreset, -- out
468 
469  -- jtag out
470  jtag => open_jtag, -- out
471  jtagdbg => open_jtagdbg, -- out
472 
473  -- trigger out
474  trgout => sig_trig, -- out
475  trgtyp => sta_trgtyp, -- out
476  trgtag => sta_trgtag, -- out
477  tagerr => sta_tagerr, -- out
478  trgshort => sta_trgshort, -- out
479  trgmask => sta_trgmask, -- out
480  rstmask => sta_rstmask, -- out
481  dismask => open_dismask, -- out
482 
483  -- status out
484  staoctet => sta_octet, -- out
485  ttup => sta_ttup, -- out
486  cntlinkrst => cnt_linkrst, -- out
487  badver => sta_badver, -- out
488 
489  -- frame and revolution signal
490  frame => sig_frame, -- out
491  frame3 => sig_frame3, -- out
492  frame9 => sig_frame9, -- out
493  frameloc => cnt_frameloc, -- out
494  divclk1 => divclk1, -- out
495  divclk2 => divclk2, -- out
496 
497  -- data out
498  octet => buf_rxoctet, -- out
499  isk => buf_rxisk, -- out
500  payload => buf_payload (76 downto 0), -- out
501  sigpayload => sig_payload, -- out
502  sigidle => sig_idle, -- out
503  cntbit2 => buf_rxcnt2, -- out
504  cntoctet => buf_rxcnto, -- out
505  cntdato => buf_rxcntd, -- out
506  cntpacket => cnt_packet, -- out 7:0
507 
508  -- regsel out
509  regsel => buf_regsel, -- out 4:0
510  usrreg => buf_usrreg, -- out 7:0
511 
512  -- debug input
513  manual => reg_imanual,
514  clrdelay => clr_idelay,
515  incdelay => set_idelay,
516  caldelay => sig_caldelay,
517 
518  -- debug output
519  bit2 => buf_rxbit2, -- out
520  bit10 => open_bit10, -- out
521  cntdelay => cnt_idelay, -- out
522  cntwidth => cnt_iwidth, -- out
523  staiddr => sta_iddr, -- out
524  starxerr => sta_rxerr, -- out
525  iddrdbg => sig_iddrdbg, -- out
526  crcdbg => sig_crcdbg ); -- out
527 
528  --- map: b2tt_payload
529  buf_id <= SUBSYSTEM & std_logic_vector(to_unsigned(FWTYPE, 4)) & id;
530  buf_ver <= std_logic_vector(to_unsigned(B2TT_VER, 8)) &
531  std_logic_vector(to_unsigned(VERSION, 16));
532 
533  map_pa: entity work.b2tt_payload
534  port map (
535  clock => clk_i,
536  id => buf_id,
537  ver => buf_ver,
538  utime => sta_utime,
539  myaddr => buf_myaddr,
540  b2clkup => sta_dcm,
541  b2ttup => sta_ttup,
542  b2plllk => b2plllk,
543  b2linkup => b2linkup,
544  b2linkwe => b2linkwe,
545  b2ttnext => fifonext,
546  b2lclk => b2lclk,
547  staictrl => sta_ictrl,
548  runreset => sig_runreset,
549  errreset => sig_errreset,
550  semreset => sig_semreset,
551  busysrc => busysrc,
552  feeerr => feeerr,
553  timerr => sta_timerr,
554  tag => sta_trgtag,
555  tagerr => sta_tagerr,
556  fifoerr => sta_fifoerr,
557  fifoful => sta_fifoful,
558  badver => sta_badver,
559  trgmask => sta_trgmask,
560  rstmask => sta_rstmask,
561  semscan => semscan,
562  semdet => semdet,
563  semcrc => semcrc,
564  semmbe => semmbe,
565  idly => buf_idly,
566  fillsig => sig_txfill,
567  regsel => buf_regsel,
568  usrreg => buf_usrreg,
569  usrdat => usrdat,
570  cntftag => cnt_ftag, -- out
571  cntb2lwe => cnt_b2lwe, -- out
572  payload => buf_txdata ); -- out
573 
574  --- map: b2tt_encode
575  sta_bsyin <= '0' when busysrc = 0 and sta_fifoful = '0' else '1';
576  sta_errin <= '0' when feeerr = 0 else '1';
577  map_encode: entity work.b2tt_encode
578  generic map (
579  FLIPACK => FLIPACK )
580  port map (
581  clock => clk_i,
582  invclock => clk_inv,
583  frame => sig_frame,
584  errreset => sig_runreset,
585  bsyin => sta_bsyin,
586  payload => buf_txdata,
587  fillsig => sig_txfill,
588 
589  -- to RJ-45
590  ackp => ackp, -- out
591  ackn => ackn, -- out
592 
593  -- debug output
594  cntbit2 => buf_txcnt2, -- out
595  cntoctet => buf_txcnto, -- out
596  isk => buf_txisk, -- out
597  octet => buf_txoctet, -- out
598  bsyup => buf_txbsyup, -- out
599  bsydn => buf_txbsydn, -- out
600  bit2 => buf_txbit2 ); -- out
601 
602  --- out
603  rsvp <= '0';
604  rsvn <= '0';
605  b2ttver <= std_logic_vector(to_unsigned(B2TT_VER, 16));
606 
607  usrreg <= buf_usrreg;
608 
609  octet <= buf_rxoctet;
610  isk <= buf_rxisk;
611  sigbit2 <= buf_rxbit2;
612  cntbit2 <= buf_rxcnt2;
613 
614  sysclk <= clk_i;
615  sysclkinv <= clk_inv;
616  dblclk <= clk_dbl;
617  revoloc <= buf_revoloc;
618  frame <= sig_frame;
619  --frame3 <= sig_frame3;
620  frame9 <= sig_frame9;
621  --frameloc <= cnt_frameloc;
622  b2clkup <= sta_dcm;
623  b2ttup <= sta_ttup;
624  utime <= sta_utime(NBITTIM-1 downto 0);
625  ctime <= sta_ctime;
626  runreset <= sig_runreset;
627  trgout <= sig_trig;
628  trgtyp <= sta_trgtyp;
629  trgtag <= sta_trgtag;
630  trgmask <= sta_trgmask;
631  rstmask <= sta_rstmask;
632 
633  fifordy <= sta_fifordy;
634 
635  rawclk <= clk_raw;
636 
637  --- chipscope
638  -- dbglink for signals to test establishing b2tt link
639  dbglink(95) <= sta_ttup;
640  dbglink(94) <= sta_octet;
641  dbglink(93) <= sig_payload;
642  dbglink(92) <= '0';
643  dbglink(91 downto 90) <= buf_rxbit2;
644  dbglink(89 downto 82) <= buf_rxoctet;
645  dbglink(81) <= buf_rxisk;
646  dbglink(80 downto 78) <= buf_rxcnt2;
647  dbglink(77 downto 73) <= buf_rxcnto;
648  dbglink(72) <= sig_idle;
649  dbglink(71) <= '0' when cnt_packet(7 downto 4) = 0 else '1';
650  dbglink(70 downto 67) <= cnt_packet(3 downto 0) when sta_ttup = '1' else
651  buf_rxcntd;
652 
653  dbglink(66) <= sig_trig;
654  dbglink(65) <= sig_runreset;
655  dbglink(64 downto 58) <= cnt_idelay;
656  dbglink(57 downto 52) <= cnt_iwidth;
657  dbglink(51 downto 43) <= sta_rxerr;
658  dbglink(42 downto 34) <= sig_crcdbg;
659  dbglink(33 downto 24) <= sig_iddrdbg;
660  dbglink(23 downto 22) <= sta_iddr;
661 
662  dbglink(21) <= buf_txbsyup;
663  dbglink(20) <= buf_txbsydn;
664  dbglink(19) <= sta_trgmask;
665 
666  dbglink(18 downto 16) <= buf_txcnt2;
667  dbglink(15 downto 12) <= buf_txcnto;
668  dbglink(11) <= '0';
669  dbglink(10 downto 9) <= buf_txbit2;
670  dbglink(8) <= buf_txisk;
671  dbglink(7 downto 0) <= buf_txoctet;
672 
673  -- dbgerr for signals to analyze error in the trigger cycle
674  dbgerr(95) <= sta_ttup; -- b2ttup
675  dbgerr(94) <= sta_octet;
676  dbgerr(93) <= sig_trig;
677  dbgerr(92) <= fifonext;
678  dbgerr(91) <= sta_fifordy;
679  dbgerr(90) <= sta_bsyin;
680  dbgerr(89) <= sta_errin;
681  dbgerr(88) <= sta_fifoerr;
682  dbgerr(87) <= sta_fifoful;
683  dbgerr(86) <= sta_tagerr;
684  dbgerr(85) <= sig_runreset;
685  dbgerr(84 downto 69) <= cnt_ftag;
686  dbgerr(68 downto 53) <= cnt_b2lwe;
687  dbgerr(52) <= b2linkup;
688  dbgerr(51) <= sta_dcm; -- b2clkup
689 
690  dbgerr(50 downto 37) <= (others => '0');
691 
692  dbgerr(36) <= buf_rxisk;
693  dbgerr(35 downto 28) <= buf_rxoctet;
694  dbgerr(27 downto 0) <= sta_trgtag(27 downto 0);
695 
696 --- b2tt: end
697 end implementation;
b2tt_injv
Definition: b2tt_injv.vhd:11
b2tt_revo
Definition: b2tt_revo.vhd:11
b2tt_encode
Definition: b2tt_encode.vhd:308
b2tt
Definition: b2tt.vhd:79
b2tt_clk.hlfclock
out hlfclockstd_logic
add
Definition: b2tt_clk_s6.vhd:42
b2tt_symbols
Definition: b2tt_symbols.vhd:17
b2tt_fifo
Definition: b2tt_fifo_s6.vhd:47
b2tt_payload
Definition: b2tt_payload.vhd:25
b2tt_clk
Definition: b2tt_clk_s6.vhd:28
b2tt_decode
Definition: b2tt_decode.vhd:1105