Belle II KLM Scint Firmware  1
b2tt_fifo Entity Reference
Inheritance diagram for b2tt_fifo:
b2tt klm_scint

Entities

implementation  architecture
 

Libraries

ieee 
unisim 

Use Clauses

std_logic_1164 
std_logic_unsigned 
numeric_std 
vcomponents 

Ports

clock   in std_logic
enfifo   in std_logic
clr   in std_logic
wr   in std_logic
din   in std_logic_vector ( 95 downto 0 )
rd   in std_logic
ready   out std_logic
dout   out std_logic_vector ( 95 downto 0 )
drd   out std_logic_vector ( 95 downto 0 )
errs   out std_logic_vector ( 3 downto 0 )
dbg   out std_logic_vector ( 17 downto 0 )
err   out std_logic
empty   out std_logic
full   out std_logic

Detailed Description

Definition at line 47 of file b2tt_fifo_s6.vhd.


The documentation for this class was generated from the following file: