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Belle II KLM Scint Firmware
1
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Entities | |
implementation | architecture |
Libraries | |
ieee | |
unisim |
Use Clauses | |
std_logic_1164 | |
std_logic_unsigned | |
numeric_std | |
vcomponents |
Generics | |
USEPLL | std_logic := ' 1 ' |
USEICTRL | std_logic := ' 0 ' |
USE254IN | std_logic := ' 0 ' |
Ports | |
clkp | in std_logic |
clkn | in std_logic |
reset | in std_logic |
rawclk | out std_logic |
clock | out std_logic |
invclock | out std_logic |
dblclock | out std_logic |
dblclockb | out std_logic |
hlfclock | out std_logic |
add | |
locked | out std_logic |
stat | out std_logic_vector ( 1 downto 0 ) |
Definition at line 28 of file b2tt_clk_s6.vhd.