implementation Architecture Reference

Processes
proc_clk_raw	( clk_raw )

Signals
clk_i	std_logic := ' 0 '
clk_inv	std_logic := ' 0 '
clk_dbl	std_logic := ' 0 '
clk_dblinv	std_logic := ' 0 '
regin	std_logic_vector ( 5 downto 0 ) := ( others = > ' 0 ' )
reg_imanual	std_logic := ' 0 '
clr_idelay	std_logic := ' 0 '
set_idelay	std_logic := ' 0 '
sig_caldelay	std_logic := ' 0 '
sta_dcm	std_logic := ' 0 '
buf_myaddr	std_logic_vector ( 19 downto 0 ) := DEFADDR
sta_ictrl	std_logic_vector ( 1 downto 0 ) := " 11 "
sta_utime	std_logic_vector ( 31 downto 0 ) := ( others = > ' 0 ' )
sta_ctime	std_logic_vector ( 26 downto 0 ) := ( others = > ' 0 ' )
sta_timerr	std_logic := ' 0 '
sig_runreset	std_logic := ' 0 '
sig_errreset	std_logic := ' 0 '
sig_trig	std_logic := ' 0 '
sta_trgtyp	std_logic_vector ( 3 downto 0 ) := ( others = > ' 0 ' )
sta_trgtag	std_logic_vector ( 31 downto 0 ) := ( others = > ' 1 ' )
sta_tagerr	std_logic := ' 0 '
sta_trgmask	std_logic := ' 0 '
sta_rstmask	std_logic := ' 0 '
sta_trgshort	std_logic := ' 0 '
sta_octet	std_logic := ' 0 '
sta_ttup	std_logic := ' 0 '
cnt_linkrst	std_logic_vector ( 7 downto 0 ) := ( others = > ' 0 ' )
sig_frame	std_logic := ' 0 '
sig_frame3	std_logic := ' 0 '
sig_frame9	std_logic := ' 0 '
cnt_frameloc	std_logic_vector ( 10 downto 0 ) := ( others = > ' 0 ' )
buf_revoloc	std_logic_vector ( 10 downto 0 ) := ( others = > ' 0 ' )
buf_payload	std_logic_vector ( 76 downto 0 ) := ( others = > ' 0 ' )
sig_payload	std_logic := ' 0 '
sig_idle	std_logic := ' 0 '
cnt_packet	std_logic_vector ( 7 downto 0 ) := ( others = > ' 0 ' )
cnt_idelay	std_logic_vector ( 6 downto 0 ) := ( others = > ' 0 ' )
cnt_iwidth	std_logic_vector ( 5 downto 0 ) := ( others = > ' 0 ' )
sta_iddr	std_logic_vector ( 1 downto 0 ) := ( others = > ' 0 ' )
sta_rxerr	std_logic_vector ( 8 downto 0 ) := ( others = > ' 0 ' )
sta_fifoful	std_logic := ' 0 '
sta_fifoemp	std_logic := ' 0 '
sta_fifoerr	std_logic := ' 0 '
sta_fifordy	std_logic := ' 0 '
sig_trgdat	std_logic_vector ( 95 downto 0 ) := ( others = > ' 0 ' )
buf_rxisk	std_logic := ' 0 '
buf_rxoctet	std_logic_vector ( 7 downto 0 ) := ( others = > ' 0 ' )
buf_rxbit2	std_logic_vector ( 1 downto 0 ) := ( others = > ' 0 ' )
buf_rxcnt2	std_logic_vector ( 2 downto 0 ) := ( others = > ' 0 ' )
buf_rxcnto	std_logic_vector ( 4 downto 0 ) := ( others = > ' 0 ' )
buf_rxcntd	std_logic_vector ( 3 downto 0 ) := ( others = > ' 0 ' )
cnt_ftag	std_logic_vector ( 15 downto 0 ) := ( others = > ' 0 ' )
cnt_b2lwe	std_logic_vector ( 15 downto 0 ) := ( others = > ' 0 ' )
buf_txdata	std_logic_vector ( 111 downto 0 ) := ( others = > ' 0 ' )
sig_txfill	std_logic
sta_bsyin	std_logic := ' 0 '
sta_errin	std_logic := ' 0 '
open_jtag	std_logic_vector ( 2 downto 0 ) := ( others = > ' 0 ' )
open_jtagdbg	std_logic_vector ( 9 downto 0 ) := ( others = > ' 0 ' )
open_clkfreq	std_logic_vector ( 23 downto 0 ) := ( others = > ' 0 ' )
open_stat	std_logic_vector ( 1 downto 0 ) := ( others = > ' 0 ' )
open_drd	std_logic_vector ( 95 downto 0 ) := ( others = > ' 0 ' )
open_dbg	std_logic_vector ( 17 downto 0 ) := ( others = > ' 0 ' )
open_bit10	std_logic_vector ( 9 downto 0 ) := ( others = > ' 0 ' )
open_clraddr	std_logic := ' 0 '
open_bsyrst	std_logic := ' 0 '
open_dismask	std_logic := ' 0 '
buf_txcnt2	std_logic_vector ( 2 downto 0 ) := ( others = > ' 0 ' )
buf_txcnto	std_logic_vector ( 3 downto 0 ) := ( others = > ' 0 ' )
buf_txisk	std_logic := ' 0 '
buf_txoctet	std_logic_vector ( 7 downto 0 ) := ( others = > ' 0 ' )
buf_txbit2	std_logic_vector ( 1 downto 0 ) := ( others = > ' 0 ' )
buf_txbsyup	std_logic := ' 0 '
buf_txbsydn	std_logic := ' 0 '
sig_iddrdbg	std_logic_vector ( 9 downto 0 ) := ( others = > ' 0 ' )
sig_crcdbg	std_logic_vector ( 8 downto 0 ) := ( others = > ' 0 ' )
sta_badver	std_logic := ' 0 '
seq_dcm	std_logic_vector ( 1 downto 0 ) := " 11 "
sig_clklost	std_logic := ' 0 '
clk_raw	std_logic := ' 0 '
sig_gtpreset	std_logic := ' 0 '
sig_semreset	std_logic := ' 0 '
buf_regsel	std_logic_vector ( 4 downto 0 ) := ( others = > ' 0 ' )
buf_usrreg	std_logic_vector ( 7 downto 0 ) := ( others = > ' 0 ' )
buf_id	std_logic_vector ( 23 downto 0 ) := ( others = > ' 0 ' )
buf_ver	std_logic_vector ( 23 downto 0 ) := ( others = > ' 0 ' )
buf_idly	std_logic_vector ( 23 downto 0 ) := ( others = > ' 0 ' )

Instantiations
map_clk	b2tt_clk <Entity b2tt_clk>
	out
map_fifo	b2tt_fifo <Entity b2tt_fifo>
map_revo	b2tt_revo <Entity b2tt_revo>
map_injv	b2tt_injv <Entity b2tt_injv>
map_decode	b2tt_decode <Entity b2tt_decode>
map_pa	b2tt_payload <Entity b2tt_payload>
map_encode	b2tt_encode <Entity b2tt_encode>

Detailed Description

Definition at line 215 of file b2tt.vhd.

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The documentation for this class was generated from the following file:

• b2tt/b2tt/b2tt.vhd