mppc_dacs_wrapper_dac088s085.vhd

library IEEE;
    use IEEE.std_logic_1164.ALL;
    use ieee.numeric_std.all;
    use ieee.std_logic_unsigned.all;
    use work.all;
----------------------------------------------------------------------------------
-- Company: University of Hawaii at Manoa
-- Engineer: Bostjan Macek
-- Create Date:    14:22:21 02/18/2014 
----------------------------------------------------------------------------------
-- Change Log:
-- 2015/05/28  Isar Morstafanezhad for DAC in RHIC RevC- 
-- 2018/12/24  Added simple clock divider inside module  -- Vasily
-- 2020/07/28  Linting only (CK)
-- 
-- Warnings:
-- XST3210: output port 'clkdiv' of 'clock_div_i' is unconnected or connected to a loadless signal (CK)

entity mppc_dacs_wrapper_dac088s085 is
    Port (
        ------------CLOCK-----------------
        clk             : in  std_logic;
        ------------DAC PARAMETERS--------
        dac_number      : in  std_logic_vector(3 downto 0);
        dac_addr        : in  std_logic_vector(3 downto 0);
        dac_value       : in  std_logic_vector(7 downto 0);
        write_strobe    : in  std_logic;
        busy            : out std_logic;
        ------------HW INTERFACE----------
        SCK_DAC         : out std_logic;
        DIN_DAC         : out std_logic;
        TDC_CS_DAC      : out std_logic_vector(9 downto 0)
    );
end mppc_dacs_wrapper_dac088s085;


architecture Behavioral of mppc_dacs_wrapper_dac088s085 is

    signal i_dac_number : std_logic_vector(3 downto 0);
    signal i_dac_addr   : std_logic_vector(3 downto 0);
    signal i_dac_value  : std_logic_vector(7 downto 0);
    signal i_dac_mask   : std_logic_vector(9 downto 0);
    signal i_cs_dac     : std_logic;    

    signal clock          : std_logic;
    signal i_write_strobe : std_logic;
    signal i_hb           : std_logic;

begin


    clk_div_i : entity work.clk_div
    generic map (
        RATIO => 32
    )
    port map (
        clk       => clk,
        rst       => '0',
        strb      => write_strobe,
        clkdiv    => clock,
        hb        => i_hb,
        sync_strb => i_write_strobe
    );


    process(clk)
    begin
        if rising_edge(clk) then
            i_dac_number <= dac_number;
            i_dac_addr   <= dac_addr;
            i_dac_value  <= dac_value;
        end if;
    end process;


    i_mppc_bias_dac088s085: entity work.mppc_bias_dac088s085 
    port map(
        clk          => clk,
        clken        => i_hb,
        dac_ch_addr  => i_dac_addr,
        dac_val      => i_dac_value,
        dac_update   => i_write_strobe,
        dac_busy     => busy,
        dac_sclk     => sck_dac,
        dac_sync_n   => i_cs_dac,
        dac_din      => din_dac
    );

    i_dac_mask <= "1111111110" when i_dac_number = x"0" else
                  "1111111101" when i_dac_number = x"1" else
                  "1111111011" when i_dac_number = x"2" else
                  "1111110111" when i_dac_number = x"3" else
                  "1111101111" when i_dac_number = x"4" else
                  "1111011111" when i_dac_number = x"5" else
                  "1110111111" when i_dac_number = x"6" else
                  "1101111111" when i_dac_number = x"7" else
                  "1011111111" when i_dac_number = x"8" else
                  "0111111111" when i_dac_number = x"9" else
                  "1111111111";

    cs_bits: for i in 0 to 9 generate
        TDC_CS_DAC(i) <= i_dac_mask(i) or i_cs_dac;
    end generate;

end Behavioral;