mppc_bias_dac088s085.vhd

library IEEE;
    use IEEE.STD_LOGIC_1164.ALL;
    use ieee.numeric_std.all;
    use ieee.std_logic_unsigned.all;
library work; 
    use work.klm_scint_pkg.all;
----------------------------------------------------------------------------------
-- Company: UH Manoa- Department of Physics
-- Engineer: Isar Mostafanezhad
-- Create Date:    15:32:50 03/30/2015 
-- Module Name:    mppc_bias_dac088s085 - Behavioral 
-- Description: FW for controlling and writing to MPPC bias DACs
--
-- Change Log:
-- 2020/07/28 - Linting only (CK)
--
-- Deficiencies:
-- 1. Need to study this module more and see if clken can be moved. Right now it's
--    8 cases behind the clken multiplexer. (CK)

entity mppc_bias_dac088s085 is
    port ( 
        clk           : in  std_logic;
        clken         : in  std_logic;
        dac_ch_addr   : in  std_logic_vector (3 downto 0);
        dac_val       : in  std_logic_vector (7 downto 0);
        dac_update    : in  std_logic;
        dac_busy      : out std_logic;
        dac_sclk      : out std_logic;
        dac_sync_n    : out std_logic;
        dac_din       : out std_logic
    );
end mppc_bias_dac088s085;


architecture Behavioral of mppc_bias_dac088s085 is

    signal addr_i   : std_logic_vector(3 downto 0);
    signal val_i    : std_logic_vector(7 downto 0);
    signal data       : slv32(1 downto 0);
    constant CMD_WTM  : std_logic_vector(15 downto 0) := "1001000000000000";

    type trim_DAC_state_type is (
        IDLE,
        SETUP_WTM,
        SET_BIT_COUNT,
        SETUP_DIN,
        SET_SCLK_LOW,
        DEC_BIT_COUNT,
        WAIT_END
    );

    signal trim_DAC_state : trim_DAC_state_type := IDLE;

begin

    process (clk, clken)
        variable data_cnt : integer range 0 to 1 := 0;
        variable bit_cnt  : integer range 0 to 31 := 31;
    begin

        if rising_edge(clk) and clken = '1' then
                
            case trim_DAC_state is

                when IDLE=>
                    dac_sclk <= '1';
                    dac_sync_n <= '1';
                    dac_din <= '0';
                    addr_i <= dac_ch_addr;
                    val_i <= dac_val;
                    if dac_update = '1' then 
                        trim_DAC_state <= SETUP_WTM;
                        dac_busy <= '1';
                    else 
                        trim_DAC_state <= IDLE;
                        dac_busy <= '0';
                    end if;

                when SETUP_WTM=>
                    dac_sync_n <= '0';
                    dac_busy <= '1';
                    data(0) <= CMD_WTM & CMD_WTM;
                    if (addr_i(3) = '0') then
                        data(1) <= CMD_WTM & '0' & addr_i(2 downto 0) & val_i & "0000";
                    else
                        data(1) <= '0' & addr_i(2 downto 0) & val_i & "0000" & CMD_WTM;
                    end if;
                    data_cnt := 0;
                    trim_DAC_state <= SET_BIT_COUNT;
          
                when SET_BIT_COUNT =>
                    dac_sclk <= '1';
                    dac_sync_n <= '0';
                    dac_din <= '0';
                    bit_cnt := 31;
                    trim_DAC_state <= SETUP_DIN;

                when SETUP_DIN =>
                    dac_sclk <= '1';
                    dac_sync_n <= '0';
                    dac_din <= data(data_cnt)(bit_cnt);
                    trim_DAC_state <= SET_SCLK_LOW;

                when SET_SCLK_LOW =>
                    dac_sclk <= '0';
                    dac_din <= data(data_cnt)(bit_cnt);
                    trim_DAC_state <= DEC_BIT_COUNT;
        
                when DEC_BIT_COUNT =>
                    if (bit_cnt /= 0) then 
                        dac_sclk <= '1';
                        dac_din <= '0';
                        bit_cnt := bit_cnt - 1;
                        trim_DAC_state <= SETUP_DIN;
                    else
                        dac_sync_n <= '1';
                        if (data_cnt = 0) then
                            data_cnt := data_cnt + 1;
                            trim_DAC_state <= SET_BIT_COUNT;
                        else
                            trim_DAC_state <= WAIT_END;
                        end if;
                    end if;
     
                when WAIT_END =>
                    dac_sclk <= '1';
                    dac_din <= '0';
                    trim_DAC_state <= IDLE;
        
                when others =>
                    trim_DAC_state <= IDLE;

            end case;
            
        end if;
    
    end process;

end Behavioral;