Belle II KLM Scint Firmware  1
klm_aurora.vhd
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49 -------------------------------------------------------------------------------------------
50 -- klm_aurora
51 --
52 --
53 -- Description: This is the top level module for a 1 2-byte lane Aurora
54 -- reference design module. This module supports the following features:
55 --
56 -- * Supports GTP
57 --
58 
59 library IEEE;
60 use IEEE.STD_LOGIC_1164.all;
61 use IEEE.STD_LOGIC_MISC.all;
62 
63 -- synthesis translate_off
64 
65 library UNISIM;
66 use UNISIM.all;
67 
68 -- synthesis translate_on
69 
70 entity klm_aurora is
71 generic(
72  SIM_GTPRESET_SPEEDUP : integer := 0;
73  CLK_CORRECT_USE : boolean := TRUE);
74 port(
75  -- LocalLink TX Interface
76  TX_D : in std_logic_vector(0 to 15);
77  TX_REM : in std_logic;
78  TX_SRC_RDY_N : in std_logic;
79  TX_SOF_N : in std_logic;
80  TX_EOF_N : in std_logic;
81  TX_DST_RDY_N : out std_logic;
82  -- LocalLink RX Interface
83  RX_D : out std_logic_vector(0 to 15);
84  RX_REM : out std_logic;
85  RX_SRC_RDY_N : out std_logic;
86  RX_SOF_N : out std_logic;
87  RX_EOF_N : out std_logic;
88  -- GTP Serial I/O
89  RXP : in std_logic;
90  RXN : in std_logic;
91  TXP : out std_logic;
92  TXN : out std_logic;
93  --GTP Reference Clock Interface
94  REFSELDYPLL : in std_logic_vector(2 downto 0);
95  REFCLK0 : in std_logic;
96  REFCLK1 : in std_logic;
97  GCLK : in std_logic;
98  -- Error Detection Interface
99  HARD_ERR : out std_logic;
100  SOFT_ERR : out std_logic;
101  FRAME_ERR : out std_logic;
102  -- Status
103  CHANNEL_UP : out std_logic;
104  LANE_UP : out std_logic;
105  -- Clock Compensation Control Interface
106  WARN_CC : in std_logic;
107  DO_CC : in std_logic;
108  -- System Interface
109  USER_CLK : in std_logic;
110  SYNC_CLK : in std_logic;
111  RESET : in std_logic;
112  POWER_DOWN : in std_logic;
113  LOOPBACK : in std_logic_vector(2 downto 0);
114  GT_RESET : in std_logic;
115  GTPCLKOUT : out std_logic;
116  RXEQMIX_IN : in std_logic_vector(1 downto 0);
117  DADDR_IN : in std_logic_vector(7 downto 0);
118  DCLK_IN : in std_logic;
119  DEN_IN : in std_logic;
120  DI_IN : in std_logic_vector(15 downto 0);
121  DRDY_OUT : out std_logic;
122  DRPDO_OUT : out std_logic_vector(15 downto 0);
123  DWE_IN : in std_logic;
124  TX_LOCK : out std_logic);
125 end klm_aurora;
126 
127 
128 architecture MAPPED of klm_aurora is
129  attribute core_generation_info : string;
130  attribute core_generation_info of MAPPED : architecture is "klm_aurora,aurora_8b10b_v5_3,{user_interface=Legacy_LL, backchannel_mode=Sidebands, c_aurora_lanes=1, c_column_used=None, c_gt_clock_1=GTPD2, c_gt_clock_2=None, c_gt_loc_1=X, c_gt_loc_10=X, c_gt_loc_11=X, c_gt_loc_12=X, c_gt_loc_13=X, c_gt_loc_14=X, c_gt_loc_15=X, c_gt_loc_16=X, c_gt_loc_17=X, c_gt_loc_18=X, c_gt_loc_19=X, c_gt_loc_2=X, c_gt_loc_20=X, c_gt_loc_21=X, c_gt_loc_22=X, c_gt_loc_23=X, c_gt_loc_24=X, c_gt_loc_25=X, c_gt_loc_26=X, c_gt_loc_27=X, c_gt_loc_28=X, c_gt_loc_29=X, c_gt_loc_3=X, c_gt_loc_30=X, c_gt_loc_31=X, c_gt_loc_32=X, c_gt_loc_33=X, c_gt_loc_34=X, c_gt_loc_35=X, c_gt_loc_36=X, c_gt_loc_37=X, c_gt_loc_38=X, c_gt_loc_39=X, c_gt_loc_4=X, c_gt_loc_40=X, c_gt_loc_41=X, c_gt_loc_42=X, c_gt_loc_43=X, c_gt_loc_44=X, c_gt_loc_45=X, c_gt_loc_46=X, c_gt_loc_47=X, c_gt_loc_48=X, c_gt_loc_5=1, c_gt_loc_6=X, c_gt_loc_7=X, c_gt_loc_8=X, c_gt_loc_9=X, c_lane_width=2, c_line_rate=2.5443, c_nfc=false, c_nfc_mode=IMM, c_refclk_frequency=127.215, c_simplex=false, c_simplex_mode=TX, c_stream=false, c_ufc=false, flow_mode=None, interface_mode=Framing, dataflow_config=Duplex}";
131 -- Component Declarations --
132 
133  component FD
134 -- synthesis translate_off
135  generic (
136  INIT : bit := '0');
137 -- synthesis translate_on
138  port (
139  Q : out std_ulogic;
140  C : in std_ulogic;
141  D : in std_ulogic);
142  end component;
143 
144  component AURORA_LANE
145  port (
146  -- GTP Interface
147  RX_DATA : in std_logic_vector(15 downto 0); -- 2-byte data bus from the GTP.
148  RX_NOT_IN_TABLE : in std_logic_vector(1 downto 0); -- Invalid 10-bit code was recieved.
149  RX_DISP_ERR : in std_logic_vector(1 downto 0); -- Disparity error detected on RX interface.
150  RX_CHAR_IS_K : in std_logic_vector(1 downto 0); -- Indicates which bytes of RX_DATA are control.
151  RX_CHAR_IS_COMMA : in std_logic_vector(1 downto 0); -- Comma received on given byte.
152  -- RX_STATUS : in std_logic_vector(5 downto 0); -- Part of GTP status and error bus.
153  RX_BUF_ERR : in std_logic; -- Overflow/Underflow of RX buffer detected.
154  TX_BUF_ERR : in std_logic; -- Overflow/Underflow of TX buffer detected.
155  RX_REALIGN : in std_logic; -- SERDES was realigned because of a new comma.
156  RX_POLARITY : out std_logic; -- Controls interpreted polarity of serial data inputs.
157  RX_RESET : out std_logic; -- Reset RX side of GTP logic.
158  TX_CHAR_IS_K : out std_logic_vector(1 downto 0); -- TX_DATA byte is a control character.
159  TX_DATA : out std_logic_vector(15 downto 0); -- 2-byte data bus to the GTP.
160  TX_RESET : out std_logic; -- Reset TX side of GTP logic.
161  -- Comma Detect Phase Align Interface
162  ENA_COMMA_ALIGN : out std_logic; -- Request comma alignment.
163  -- TX_LL Interface
164  GEN_SCP : in std_logic; -- SCP generation request from TX_LL.
165  GEN_ECP : in std_logic; -- ECP generation request from TX_LL.
166  GEN_PAD : in std_logic; -- PAD generation request from TX_LL.
167  TX_PE_DATA : in std_logic_vector(0 to 15); -- Data from TX_LL to send over lane.
168  TX_PE_DATA_V : in std_logic; -- Indicates TX_PE_DATA is Valid.
169  GEN_CC : in std_logic; -- CC generation request from TX_LL.
170  -- RX_LL Interface
171  RX_PAD : out std_logic; -- Indicates lane received PAD.
172  RX_PE_DATA : out std_logic_vector(0 to 15); -- RX data from lane to RX_LL.
173  RX_PE_DATA_V : out std_logic; -- RX_PE_DATA is data, not control symbol.
174  RX_SCP : out std_logic; -- Indicates lane received SCP.
175  RX_ECP : out std_logic; -- Indicates lane received ECP.
176  -- Global Logic Interface
177  GEN_A : in std_logic; -- 'A character' generation request from Global Logic.
178  GEN_K : in std_logic_vector(0 to 1); -- 'K character' generation request from Global Logic.
179  GEN_R : in std_logic_vector(0 to 1); -- 'R character' generation request from Global Logic.
180  GEN_V : in std_logic_vector(0 to 1); -- Verification data generation request.
181  LANE_UP : out std_logic; -- Lane is ready for bonding and verification.
182  SOFT_ERR : out std_logic; -- Soft error detected.
183  HARD_ERR : out std_logic; -- Hard error detected.
184  CHANNEL_BOND_LOAD : out std_logic; -- Channel Bonding done code received.
185  GOT_A : out std_logic_vector(0 to 1); -- Indicates lane recieved 'A character' bytes.
186  GOT_V : out std_logic; -- Verification symbols received.
187  -- System Interface
188  USER_CLK : in std_logic; -- System clock for all non-GTP Aurora Logic.
189  RESET_SYMGEN : in std_logic; -- Reset the SYM_GEN module.
190  RESET : in std_logic); -- Reset the lane.
191  end component;
192 
193  component GTP_WRAPPER
194  generic(
195  SIM_GTPRESET_SPEEDUP : integer := 0; --Set to 1 to speed up sim reset
196  CLK_CORRECT_USE : boolean := TRUE);--Set to true to use clock correction
197  port(
198  ENMCOMMAALIGN_IN : in std_logic;
199  ENPCOMMAALIGN_IN : in std_logic;
200  LOOPBACK_IN : in std_logic_vector (2 downto 0);
201  RXPOLARITY_IN : in std_logic;
202  RXRESET_IN : in std_logic;
203  TXCHARISK_IN : in std_logic_vector (1 downto 0);
204  TXDATA_IN : in std_logic_vector (15 downto 0);
205  GTPRESET_IN : in std_logic;
206  TXRESET_IN : in std_logic;
207  RXBUFERR_OUT : out std_logic;
208  RXCHARISCOMMA_OUT : out std_logic_vector (1 downto 0);
209  RXCHARISK_OUT : out std_logic_vector (1 downto 0);
210  RXDATA_OUT : out std_logic_vector (15 downto 0);
211  RXDISPERR_OUT : out std_logic_vector (1 downto 0);
212  RXNOTINTABLE_OUT : out std_logic_vector (1 downto 0);
213  RXREALIGN_OUT : out std_logic;
214  RXRECCLK1_OUT : out std_logic;
215  RXRECCLK2_OUT : out std_logic;
216  TXBUFERR_OUT : out std_logic;
217  PLLLKDET_OUT : out std_logic;
218  GTPCLKOUT_OUT : out std_logic_vector (1 downto 0);
219  RXEQMIX_IN : in std_logic_vector(1 downto 0);
220  DADDR_IN : in std_logic_vector(7 downto 0);
221  DCLK_IN : in std_logic;
222  DEN_IN : in std_logic;
223  DI_IN : in std_logic_vector(15 downto 0);
224  DRDY_OUT : out std_logic;
225  DRPDO_OUT : out std_logic_vector(15 downto 0);
226  DWE_IN : in std_logic;
227  RX1N_IN : in std_logic;
228  RX1P_IN : in std_logic;
229  TX1N_OUT : out std_logic;
230  TX1P_OUT : out std_logic;
231  TXUSRCLK_IN : in std_logic;
232  TXUSRCLK2_IN : in std_logic;
233  RXUSRCLK_IN : in std_logic;
234  RXUSRCLK2_IN : in std_logic;
235  REFSELDYPLL : in std_logic_vector(2 downto 0);
236  REFCLK0 : in std_logic;
237  REFCLK1 : in std_logic;
238  GCLK : in std_logic;
239  RXCHARISCOMMA_OUT_unused : out std_logic_vector (1 downto 0);
240  RXCHARISK_OUT_unused : out std_logic_vector (1 downto 0);
241  RXDISPERR_OUT_unused : out std_logic_vector (1 downto 0);
242  RXNOTINTABLE_OUT_unused : out std_logic_vector (1 downto 0);
243  ------------------- Receive Ports - Channel Bonding Ports -----------------
244  RXREALIGN_OUT_unused : out std_logic;
245  RXDATA_OUT_unused : out std_logic_vector (15 downto 0);
246  RX1N_IN_unused : in std_logic;
247  RX1P_IN_unused : in std_logic;
248  RXBUFERR_OUT_unused : out std_logic_vector(2 downto 0);
249  TXBUFERR_OUT_unused : out std_logic_vector(1 downto 0);
250  CHBONDDONE_OUT_unused : out std_logic;
251  TX1N_OUT_unused : out std_logic;
252  TX1P_OUT_unused : out std_logic;
253  POWERDOWN_IN : in std_logic);
254  end component;
255 
256  component BUFG
257  port(
258  O : out STD_ULOGIC;
259  I : in STD_ULOGIC);
260  end component;
261 
262  component GLOBAL_LOGIC
263  port(
264  -- GTP Interface
265  EN_CHAN_SYNC : out std_logic;
266  -- Aurora Lane Interface
267  LANE_UP : in std_logic;
268  SOFT_ERR : in std_logic;
269  HARD_ERR : in std_logic;
270  GOT_V : in std_logic;
271  GEN_A : out std_logic;
272  GEN_K : out std_logic_vector(0 to 1);
273  GEN_R : out std_logic_vector(0 to 1);
274  GEN_V : out std_logic_vector(0 to 1);
275  RESET_LANES : out std_logic;
276  -- System Interface
277  USER_CLK : in std_logic;
278  RESET : in std_logic;
279  POWER_DOWN : in std_logic;
280  CHANNEL_UP : out std_logic;
281  START_RX : out std_logic;
282  CHANNEL_SOFT_ERR : out std_logic;
283  CHANNEL_HARD_ERR : out std_logic);
284  end component;
285 
286  component TX_LL
287  port(
288  -- LocalLink PDU Interface
289  TX_D : in std_logic_vector(0 to 15);
290  TX_REM : in std_logic;
291  TX_SRC_RDY_N : in std_logic;
292  TX_SOF_N : in std_logic;
293  TX_EOF_N : in std_logic;
294  TX_DST_RDY_N : out std_logic;
295  -- Clock Compensation Interface
296  WARN_CC : in std_logic;
297  DO_CC : in std_logic;
298  -- Global Logic Interface
299  CHANNEL_UP : in std_logic;
300  -- Aurora Lane Interface
301  GEN_SCP : out std_logic;
302  GEN_ECP : out std_logic;
303  TX_PE_DATA_V : out std_logic;
304  GEN_PAD : out std_logic;
305  TX_PE_DATA : out std_logic_vector(0 to 15);
306  GEN_CC : out std_logic;
307  -- System Interface
308  USER_CLK : in std_logic);
309  end component;
310 
311  component RX_LL
312  port(
313  -- LocalLink PDU Interface
314  RX_D : out std_logic_vector(0 to 15);
315  RX_REM : out std_logic;
316  RX_SRC_RDY_N : out std_logic;
317  RX_SOF_N : out std_logic;
318  RX_EOF_N : out std_logic;
319  -- Global Logic Interface
320  START_RX : in std_logic;
321  -- Aurora Lane Interface
322  RX_PAD : in std_logic;
323  RX_PE_DATA : in std_logic_vector(0 to 15);
324  RX_PE_DATA_V : in std_logic;
325  RX_SCP : in std_logic;
326  RX_ECP : in std_logic;
327  -- Error Interface
328  FRAME_ERR : out std_logic;
329  -- System Interface
330  USER_CLK : in std_logic);
331  end component;
332 
333 -- Signal Declarations --
334  signal TX1N_OUT_unused : std_logic;
335  signal TX1P_OUT_unused : std_logic;
336  signal RX1N_IN_unused : std_logic;
337  signal RX1P_IN_unused : std_logic;
338  signal rx_char_is_comma_i_unused : std_logic_vector(1 downto 0);
339  signal rx_char_is_k_i_unused : std_logic_vector(1 downto 0);
340  signal rx_data_i_unused : std_logic_vector(15 downto 0);
341  signal rx_disp_err_i_unused : std_logic_vector(1 downto 0);
342  signal rx_not_in_table_i_unused : std_logic_vector(1 downto 0);
343  signal rx_realign_i_unused : std_logic;
344  signal ch_bond_done_i_unused : std_logic;
345  signal rx_buf_err_i_unused : std_logic_vector(2 downto 0);
346  signal tx_buf_err_i_unused : std_logic_vector(1 downto 0);
347  signal ch_bond_done_r1 : std_logic;
348  signal ch_bond_done_r2 : std_logic;
349  -- signal ch_bond_load_not_used_i : std_logic;
350  signal channel_bond_load_i : std_logic;
351  signal channel_up_i : std_logic;
352  signal chbondo_not_used_i : std_logic_vector(4 downto 0);
353  signal en_chan_sync_i : std_logic;
354  signal ena_comma_align_i : std_logic;
355  signal gen_a_i : std_logic;
356  signal gen_cc_i : std_logic;
357  signal gen_ecp_i : std_logic;
358  signal gen_k_i : std_logic_vector(0 to 1);
359  signal gen_pad_i : std_logic;
360  signal gen_r_i : std_logic_vector(0 to 1);
361  signal gen_scp_i : std_logic;
362  signal gen_v_i : std_logic_vector(0 to 1);
363  signal got_a_i : std_logic_vector(0 to 1);
364  signal got_v_i : std_logic;
365  signal hard_err_i : std_logic;
366  signal lane_up_i : std_logic;
367  signal master_chbondo_i : std_logic;
368  signal open_rx_char_is_comma_i : std_logic_vector(5 downto 0);
369  signal open_rx_char_is_k_i : std_logic_vector(5 downto 0);
370  signal open_rx_comma_det_i : std_logic;
371  signal open_rx_data_i : std_logic_vector(47 downto 0);
372  signal open_rx_disp_err_i : std_logic_vector(5 downto 0);
373  signal open_rx_loss_of_sync_i : std_logic_vector(1 downto 0);
374  signal open_rx_not_in_table_i : std_logic_vector(5 downto 0);
375  signal open_rx_rec1_clk_i : std_logic;
376  signal open_rx_rec2_clk_i : std_logic;
377  signal open_rx_run_disp_i : std_logic_vector(7 downto 0);
378  signal open_tx_k_err_i : std_logic_vector(7 downto 0);
379  signal open_tx_run_disp_i : std_logic_vector(7 downto 0);
380  signal raw_gtpclkout_i : std_logic_vector(1 downto 0);
381  signal reset_lanes_i : std_logic;
382  signal rx_buf_err_i : std_logic;
383  signal rx_char_is_comma_i : std_logic_vector(1 downto 0);
384  signal rx_char_is_comma_gtp_i : std_logic_vector(7 downto 0);
385  signal rx_char_is_k_i : std_logic_vector(1 downto 0);
386  signal rx_char_is_k_gtp_i : std_logic_vector(7 downto 0);
387  signal rx_clk_cor_cnt_i : std_logic_vector(2 downto 0);
388  signal rx_data_0_vec : std_logic_vector(63 downto 0);
389  signal rx_data_i : std_logic_vector(15 downto 0);
390  signal rx_data_gtp_i : std_logic_vector(63 downto 0);
391  signal rx_disp_err_i : std_logic_vector(1 downto 0);
392  signal rx_disp_err_gtp_i : std_logic_vector(7 downto 0);
393  signal rx_ecp_i : std_logic;
394  signal rx_not_in_table_i : std_logic_vector(1 downto 0);
395  signal rx_not_in_table_gtp_i : std_logic_vector(7 downto 0);
396  signal rx_pad_i : std_logic;
397  signal rx_pe_data_i : std_logic_vector(0 to 15);
398  signal rx_pe_data_v_i : std_logic;
399  signal rx_polarity_i : std_logic;
400  signal rx_realign_i : std_logic;
401  signal rx_reset_i : std_logic;
402  signal rx_scp_i : std_logic;
403  signal rxchariscomma_0_vec : std_logic_vector(7 downto 0);
404  signal rxcharisk_0_vec : std_logic_vector(7 downto 0);
405  signal rxdisperr_0_vec : std_logic_vector(7 downto 0);
406  signal rxmclk_out_not_used_i : std_logic;
407  signal rxnotintable_0_vec : std_logic_vector(7 downto 0);
408  signal rxpcshclkout_not_used_i : std_logic;
409  signal soft_err_i : std_logic;
410  signal start_rx_i : std_logic;
411  signal tied_to_ground_i : std_logic;
412  -- signal tied_to_ground_vec_i : std_logic_vector(47 downto 0);
413  signal tied_to_vcc_i : std_logic;
414  signal tx_buf_err_i : std_logic;
415  signal tx_char_is_k_i : std_logic_vector(1 downto 0);
416  signal tx_char_is_k_gtp_i : std_logic_vector(7 downto 0);
417  signal tx_data_i : std_logic_vector(15 downto 0);
418  signal tx_data_gtp_i : std_logic_vector(63 downto 0);
419  signal tx_int_data_width_i : std_logic_vector(1 downto 0);
420  signal tx_lock_i : std_logic;
421  signal tx_pe_data_i : std_logic_vector(0 to 15);
422  signal tx_pe_data_v_i : std_logic;
423  signal tx_reset_i : std_logic;
424  signal txcharisk_lane_0_i : std_logic_vector(7 downto 0);
425  signal txdata_lane_0_i : std_logic_vector(63 downto 0);
426  signal txoutclk2_out_not_used_i : std_logic;
427  signal txpcshclkout_not_used_i : std_logic;
428  signal tied_to_gnd_vec_i : std_logic_vector(0 to 15);
429 begin
430 
431 -- Main Body of Code --
432  -- Tie off top level constants
433  tied_to_gnd_vec_i <= (others => '0');
434  -- tied_to_ground_vec_i <= (others => '0');
435  tied_to_ground_i <= '0';
436  tied_to_vcc_i <= '1';
437  -- Connect top level logic
438  CHANNEL_UP <= channel_up_i;
439  GTPCLKOUT <= raw_gtpclkout_i(0);
440  -- Connect TX_LOCK to tx_lock_i from lane 0
441  TX_LOCK <= tx_lock_i;
442  -- Instantiate Lane 0 --
443  LANE_UP <= lane_up_i;
444 
445  aurora_lane_0_i : AURORA_LANE
446  port map (
447  -- GTP Interface
448  RX_DATA => rx_data_i(15 downto 0),
449  RX_NOT_IN_TABLE => rx_not_in_table_i(1 downto 0),
450  RX_DISP_ERR => rx_disp_err_i(1 downto 0),
451  RX_CHAR_IS_K => rx_char_is_k_i(1 downto 0),
452  RX_CHAR_IS_COMMA => rx_char_is_comma_i(1 downto 0),
453  -- RX_STATUS => tied_to_ground_vec_i(5 downto 0),
454  TX_BUF_ERR => tx_buf_err_i,
455  RX_BUF_ERR => rx_buf_err_i,
456  RX_REALIGN => rx_realign_i,
457  RX_POLARITY => rx_polarity_i,
458  RX_RESET => rx_reset_i,
459  TX_CHAR_IS_K => tx_char_is_k_i(1 downto 0),
460  TX_DATA => tx_data_i(15 downto 0),
461  TX_RESET => tx_reset_i,
462  -- Comma Detect Phase Align Interface
463  ENA_COMMA_ALIGN => ena_comma_align_i,
464  -- TX_LL Interface
465  GEN_SCP => gen_scp_i,
466  GEN_ECP => gen_ecp_i,
467  GEN_PAD => gen_pad_i,
468  TX_PE_DATA => tx_pe_data_i(0 to 15),
469  TX_PE_DATA_V => tx_pe_data_v_i,
470  GEN_CC => gen_cc_i,
471  -- RX_LL Interface
472  RX_PAD => rx_pad_i,
473  RX_PE_DATA => rx_pe_data_i(0 to 15),
474  RX_PE_DATA_V => rx_pe_data_v_i,
475  RX_SCP => rx_scp_i,
476  RX_ECP => rx_ecp_i,
477  -- Global Logic Interface
478  GEN_A => gen_a_i,
479  GEN_K => gen_k_i(0 to 1),
480  GEN_R => gen_r_i(0 to 1),
481  GEN_V => gen_v_i(0 to 1),
482  LANE_UP => lane_up_i,
483  SOFT_ERR => soft_err_i,
484  HARD_ERR => hard_err_i,
485  -- CHANNEL_BOND_LOAD => ch_bond_load_not_used_i,
486  GOT_A => got_a_i(0 to 1),
487  GOT_V => got_v_i,
488  -- System Interface
489  USER_CLK => USER_CLK,
490  RESET_SYMGEN => RESET,
491  RESET => reset_lanes_i);
492 
493  -- Instantiate GTP Wrapper --
494 
495  gtp_wrapper_i : GTP_WRAPPER
496  generic map(
497  SIM_GTPRESET_SPEEDUP => SIM_GTPRESET_SPEEDUP,
498  CLK_CORRECT_USE => TRUE)--CLK_CORRECT_USE)--! Don't mess with transceiver. Clocking issue if no clock correction without phase alignment.
499  port map(
500  ENMCOMMAALIGN_IN => ena_comma_align_i,
501  ENPCOMMAALIGN_IN => ena_comma_align_i,
502  LOOPBACK_IN => LOOPBACK,
503  -- Aurora Lane Interface
504  RXPOLARITY_IN => rx_polarity_i,
505  RXRESET_IN => rx_reset_i,
506  TXCHARISK_IN => tx_char_is_k_i(1 downto 0),
507  TXDATA_IN => tx_data_i(15 downto 0),
508  GTPRESET_IN => GT_RESET,
509  TXRESET_IN => tx_reset_i,
510  RXBUFERR_OUT => rx_buf_err_i,
511  RXCHARISCOMMA_OUT => rx_char_is_comma_i(1 downto 0),
512  RXCHARISK_OUT => rx_char_is_k_i(1 downto 0),
513  RXDATA_OUT => rx_data_i(15 downto 0),
514  RXDISPERR_OUT => rx_disp_err_i(1 downto 0),
515  RXNOTINTABLE_OUT => rx_not_in_table_i(1 downto 0),
516  RXREALIGN_OUT => rx_realign_i,
517  RXRECCLK1_OUT => open_rx_rec1_clk_i,
518  RXRECCLK2_OUT => open_rx_rec2_clk_i,
519  TXBUFERR_OUT => tx_buf_err_i,
520  -- Serial IO
521  RXEQMIX_IN => RXEQMIX_IN,
522  DADDR_IN => DADDR_IN,
523  DCLK_IN => DCLK_IN,
524  DEN_IN => DEN_IN,
525  DI_IN => DI_IN,
526  DRDY_OUT => DRDY_OUT,
527  DRPDO_OUT => DRPDO_OUT,
528  DWE_IN => DWE_IN,
529  RX1N_IN => RXN,
530  RX1P_IN => RXP,
531  TX1N_OUT => TXN,
532  TX1P_OUT => TXP,
533  PLLLKDET_OUT => tx_lock_i,
534  GTPCLKOUT_OUT => raw_gtpclkout_i,
535  -- Reference Clocks and User Clock
536  RXUSRCLK_IN => SYNC_CLK,
537  RXUSRCLK2_IN => USER_CLK,
538  TXUSRCLK_IN => SYNC_CLK,
539  TXUSRCLK2_IN => USER_CLK,
540  REFSELDYPLL => REFSELDYPLL,
541  REFCLK0 => REFCLK0,
542  REFCLK1 => REFCLK1,
543  GCLK => GCLK,
544  RXCHARISCOMMA_OUT_unused => rx_char_is_comma_i_unused(1 downto 0),
545  RXCHARISK_OUT_unused => rx_char_is_k_i_unused(1 downto 0),
546  RXDISPERR_OUT_unused => rx_disp_err_i_unused(1 downto 0),
547  RXNOTINTABLE_OUT_unused => rx_not_in_table_i_unused(1 downto 0),
548  ----------------- Receive Ports - Channel Bonding Ports -----------------
549  RXREALIGN_OUT_unused => rx_realign_i_unused,
550  RXDATA_OUT_unused => rx_data_i_unused(15 downto 0),
551  RX1N_IN_unused => RX1N_IN_unused,
552  RX1P_IN_unused => RX1P_IN_unused,
553  RXBUFERR_OUT_unused => rx_buf_err_i_unused,
554  TXBUFERR_OUT_unused => tx_buf_err_i_unused,
555  CHBONDDONE_OUT_unused => ch_bond_done_i_unused,
556  TX1N_OUT_unused => TX1N_OUT_unused,
557  TX1P_OUT_unused => TX1P_OUT_unused,
558  POWERDOWN_IN => POWER_DOWN
559  );
560 
561  -- Instantiate Global Logic to combine Lanes into a Channel --
562  global_logic_i : GLOBAL_LOGIC
563  port map (
564  -- GTP Interface
565  EN_CHAN_SYNC => en_chan_sync_i,
566  -- Aurora Lane Interface
567  LANE_UP => lane_up_i,
568  SOFT_ERR => soft_err_i,
569  HARD_ERR => hard_err_i,
570  GOT_V => got_v_i,
571  GEN_A => gen_a_i,
572  GEN_K => gen_k_i,
573  GEN_R => gen_r_i,
574  GEN_V => gen_v_i,
575  RESET_LANES => reset_lanes_i,
576  -- System Interface
577  USER_CLK => USER_CLK,
578  RESET => RESET,
579  POWER_DOWN => POWER_DOWN,
580  CHANNEL_UP => channel_up_i,
581  START_RX => start_rx_i,
582  CHANNEL_SOFT_ERR => SOFT_ERR,
583  CHANNEL_HARD_ERR => HARD_ERR
584  );
585 
586  -- Instantiate TX_LL --
587  tx_ll_i : TX_LL
588  port map(
589  -- LocalLink PDU Interface
590  TX_D => TX_D,
591  TX_REM => TX_REM,
592  TX_SRC_RDY_N => TX_SRC_RDY_N,
593  TX_SOF_N => TX_SOF_N,
594  TX_EOF_N => TX_EOF_N,
595  TX_DST_RDY_N => TX_DST_RDY_N,
596  -- Clock Compenstaion Interface
597  WARN_CC => WARN_CC,
598  DO_CC => DO_CC,
599  -- Global Logic Interface
600  CHANNEL_UP => channel_up_i,
601  -- Aurora Lane Interface
602  GEN_SCP => gen_scp_i,
603  GEN_ECP => gen_ecp_i,
604  TX_PE_DATA_V => tx_pe_data_v_i,
605  GEN_PAD => gen_pad_i,
606  TX_PE_DATA => tx_pe_data_i,
607  GEN_CC => gen_cc_i,
608  -- System Interface
609  USER_CLK => USER_CLK
610  );
611 
612 
613  -- Instantiate RX_LL --
614  rx_ll_i : RX_LL
615  port map (
616  -- LocalLink PDU Interface
617  RX_D => RX_D,
618  RX_REM => RX_REM,
619  RX_SRC_RDY_N => RX_SRC_RDY_N,
620  RX_SOF_N => RX_SOF_N,
621  RX_EOF_N => RX_EOF_N,
622  -- Global Logic Interface
623  START_RX => start_rx_i,
624  -- Aurora Lane Interface
625  RX_PAD => rx_pad_i,
626  RX_PE_DATA => rx_pe_data_i,
627  RX_PE_DATA_V => rx_pe_data_v_i,
628  RX_SCP => rx_scp_i,
629  RX_ECP => rx_ecp_i,
630  -- Error Interface
631  FRAME_ERR => FRAME_ERR,
632  -- System Interface
633  USER_CLK => USER_CLK
634  );
635 
636 end MAPPED;
klm_aurora
Definition: klm_aurora.vhd:70
RX_LL
Definition: rx_ll.vhd:65
TX_LL
Definition: tx_ll.vhd:63
GTP_WRAPPER
Definition: transceiver_wrapper.vhd:73
AURORA_LANE
Definition: aurora_lane.vhd:67
GLOBAL_LOGIC
Definition: global_logic.vhd:63