MAPPED Architecture Reference

Components
FD
AURORA_LANE	<Entity AURORA_LANE>
GTP_WRAPPER	<Entity GTP_WRAPPER>
BUFG
GLOBAL_LOGIC	<Entity GLOBAL_LOGIC>
TX_LL	<Entity TX_LL>
RX_LL	<Entity RX_LL>

Signals
TX1N_OUT_unused	std_logic
TX1P_OUT_unused	std_logic
RX1N_IN_unused	std_logic
RX1P_IN_unused	std_logic
rx_char_is_comma_i_unused	std_logic_vector ( 1 downto 0 )
rx_char_is_k_i_unused	std_logic_vector ( 1 downto 0 )
rx_data_i_unused	std_logic_vector ( 15 downto 0 )
rx_disp_err_i_unused	std_logic_vector ( 1 downto 0 )
rx_not_in_table_i_unused	std_logic_vector ( 1 downto 0 )
rx_realign_i_unused	std_logic
ch_bond_done_i_unused	std_logic
rx_buf_err_i_unused	std_logic_vector ( 2 downto 0 )
tx_buf_err_i_unused	std_logic_vector ( 1 downto 0 )
ch_bond_done_r1	std_logic
ch_bond_done_r2	std_logic
channel_bond_load_i	std_logic
channel_up_i	std_logic
chbondo_not_used_i	std_logic_vector ( 4 downto 0 )
en_chan_sync_i	std_logic
ena_comma_align_i	std_logic
gen_a_i	std_logic
gen_cc_i	std_logic
gen_ecp_i	std_logic
gen_k_i	std_logic_vector ( 0 to 1 )
gen_pad_i	std_logic
gen_r_i	std_logic_vector ( 0 to 1 )
gen_scp_i	std_logic
gen_v_i	std_logic_vector ( 0 to 1 )
got_a_i	std_logic_vector ( 0 to 1 )
got_v_i	std_logic
hard_err_i	std_logic
lane_up_i	std_logic
master_chbondo_i	std_logic
open_rx_char_is_comma_i	std_logic_vector ( 5 downto 0 )
open_rx_char_is_k_i	std_logic_vector ( 5 downto 0 )
open_rx_comma_det_i	std_logic
open_rx_data_i	std_logic_vector ( 47 downto 0 )
open_rx_disp_err_i	std_logic_vector ( 5 downto 0 )
open_rx_loss_of_sync_i	std_logic_vector ( 1 downto 0 )
open_rx_not_in_table_i	std_logic_vector ( 5 downto 0 )
open_rx_rec1_clk_i	std_logic
open_rx_rec2_clk_i	std_logic
open_rx_run_disp_i	std_logic_vector ( 7 downto 0 )
open_tx_k_err_i	std_logic_vector ( 7 downto 0 )
open_tx_run_disp_i	std_logic_vector ( 7 downto 0 )
raw_gtpclkout_i	std_logic_vector ( 1 downto 0 )
reset_lanes_i	std_logic
rx_buf_err_i	std_logic
rx_char_is_comma_i	std_logic_vector ( 1 downto 0 )
rx_char_is_comma_gtp_i	std_logic_vector ( 7 downto 0 )
rx_char_is_k_i	std_logic_vector ( 1 downto 0 )
rx_char_is_k_gtp_i	std_logic_vector ( 7 downto 0 )
rx_clk_cor_cnt_i	std_logic_vector ( 2 downto 0 )
rx_data_0_vec	std_logic_vector ( 63 downto 0 )
rx_data_i	std_logic_vector ( 15 downto 0 )
rx_data_gtp_i	std_logic_vector ( 63 downto 0 )
rx_disp_err_i	std_logic_vector ( 1 downto 0 )
rx_disp_err_gtp_i	std_logic_vector ( 7 downto 0 )
rx_ecp_i	std_logic
rx_not_in_table_i	std_logic_vector ( 1 downto 0 )
rx_not_in_table_gtp_i	std_logic_vector ( 7 downto 0 )
rx_pad_i	std_logic
rx_pe_data_i	std_logic_vector ( 0 to 15 )
rx_pe_data_v_i	std_logic
rx_polarity_i	std_logic
rx_realign_i	std_logic
rx_reset_i	std_logic
rx_scp_i	std_logic
rxchariscomma_0_vec	std_logic_vector ( 7 downto 0 )
rxcharisk_0_vec	std_logic_vector ( 7 downto 0 )
rxdisperr_0_vec	std_logic_vector ( 7 downto 0 )
rxmclk_out_not_used_i	std_logic
rxnotintable_0_vec	std_logic_vector ( 7 downto 0 )
rxpcshclkout_not_used_i	std_logic
soft_err_i	std_logic
start_rx_i	std_logic
tied_to_ground_i	std_logic
tied_to_vcc_i	std_logic
tx_buf_err_i	std_logic
tx_char_is_k_i	std_logic_vector ( 1 downto 0 )
tx_char_is_k_gtp_i	std_logic_vector ( 7 downto 0 )
tx_data_i	std_logic_vector ( 15 downto 0 )
tx_data_gtp_i	std_logic_vector ( 63 downto 0 )
tx_int_data_width_i	std_logic_vector ( 1 downto 0 )
tx_lock_i	std_logic
tx_pe_data_i	std_logic_vector ( 0 to 15 )
tx_pe_data_v_i	std_logic
tx_reset_i	std_logic
txcharisk_lane_0_i	std_logic_vector ( 7 downto 0 )
txdata_lane_0_i	std_logic_vector ( 63 downto 0 )
txoutclk2_out_not_used_i	std_logic
txpcshclkout_not_used_i	std_logic
tied_to_gnd_vec_i	std_logic_vector ( 0 to 15 )

Attributes
core_generation_info	string
core_generation_info	MAPPED : architecture is " klm_aurora , aurora_8b10b_v5_3 , {user_interface = Legacy_LL , backchannel_mode = Sidebands , c_aurora_lanes = 1 , c_column_used = None , c_gt_clock_1 = GTPD2 , c_gt_clock_2 = None , c_gt_loc_1 = X , c_gt_loc_10 = X , c_gt_loc_11 = X , c_gt_loc_12 = X , c_gt_loc_13 = X , c_gt_loc_14 = X , c_gt_loc_15 = X , c_gt_loc_16 = X , c_gt_loc_17 = X , c_gt_loc_18 = X , c_gt_loc_19 = X , c_gt_loc_2 = X , c_gt_loc_20 = X , c_gt_loc_21 = X , c_gt_loc_22 = X , c_gt_loc_23 = X , c_gt_loc_24 = X , c_gt_loc_25 = X , c_gt_loc_26 = X , c_gt_loc_27 = X , c_gt_loc_28 = X , c_gt_loc_29 = X , c_gt_loc_3 = X , c_gt_loc_30 = X , c_gt_loc_31 = X , c_gt_loc_32 = X , c_gt_loc_33 = X , c_gt_loc_34 = X , c_gt_loc_35 = X , c_gt_loc_36 = X , c_gt_loc_37 = X , c_gt_loc_38 = X , c_gt_loc_39 = X , c_gt_loc_4 = X , c_gt_loc_40 = X , c_gt_loc_41 = X , c_gt_loc_42 = X , c_gt_loc_43 = X , c_gt_loc_44 = X , c_gt_loc_45 = X , c_gt_loc_46 = X , c_gt_loc_47 = X , c_gt_loc_48 = X , c_gt_loc_5 = 1 , c_gt_loc_6 = X , c_gt_loc_7 = X , c_gt_loc_8 = X , c_gt_loc_9 = X , c_lane_width = 2 , c_line_rate = 2.5443 , c_nfc = false , c_nfc_mode = IMM , c_refclk_frequency = 127.215 , c_simplex = false , c_simplex_mode = TX , c_stream = false , c_ufc = false , flow_mode = None , interface_mode = Framing , dataflow_config = Duplex} "

Instantiations
aurora_lane_0_i	AURORA_LANE <Entity AURORA_LANE>
gtp_wrapper_i	GTP_WRAPPER <Entity GTP_WRAPPER>
global_logic_i	GLOBAL_LOGIC <Entity GLOBAL_LOGIC>
tx_ll_i	TX_LL <Entity TX_LL>
rx_ll_i	RX_LL <Entity RX_LL>

Detailed Description

Definition at line 128 of file klm_aurora.vhd.

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The documentation for this class was generated from the following file:

• klm_aurora/source/klm_aurora.vhd