GLOBAL_LOGIC Entity Reference

Inheritance diagram for GLOBAL_LOGIC:

Entities
MAPPED	architecture

Libraries
IEEE

Use Clauses
STD_LOGIC_1164

Ports
EN_CHAN_SYNC	out std_logic
LANE_UP	in std_logic
SOFT_ERR	in std_logic
HARD_ERR	in std_logic
GOT_V	in std_logic
GEN_A	out std_logic
GEN_K	out std_logic_vector ( 0 to 1 )
GEN_R	out std_logic_vector ( 0 to 1 )
GEN_V	out std_logic_vector ( 0 to 1 )
RESET_LANES	out std_logic
USER_CLK	in std_logic
RESET	in std_logic
POWER_DOWN	in std_logic
CHANNEL_UP	out std_logic
START_RX	out std_logic
CHANNEL_SOFT_ERR	out std_logic
CHANNEL_HARD_ERR	out std_logic

Detailed Description

Definition at line 63 of file global_logic.vhd.

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The documentation for this class was generated from the following file:

• klm_aurora/source/global_logic.vhd