klm_aurora Entity Reference

Inheritance diagram for klm_aurora:

Entities
MAPPED	architecture

Libraries
IEEE
UNISIM

Use Clauses
STD_LOGIC_1164
STD_LOGIC_MISC
all

Generics
SIM_GTPRESET_SPEEDUP	integer := 0
CLK_CORRECT_USE	boolean := TRUE

Ports
TX_D	in std_logic_vector ( 0 to 15 )
TX_REM	in std_logic
TX_SRC_RDY_N	in std_logic
TX_SOF_N	in std_logic
TX_EOF_N	in std_logic
TX_DST_RDY_N	out std_logic
RX_D	out std_logic_vector ( 0 to 15 )
RX_REM	out std_logic
RX_SRC_RDY_N	out std_logic
RX_SOF_N	out std_logic
RX_EOF_N	out std_logic
RXP	in std_logic
RXN	in std_logic
TXP	out std_logic
TXN	out std_logic
REFSELDYPLL	in std_logic_vector ( 2 downto 0 )
REFCLK0	in std_logic
REFCLK1	in std_logic
GCLK	in std_logic
HARD_ERR	out std_logic
SOFT_ERR	out std_logic
FRAME_ERR	out std_logic
CHANNEL_UP	out std_logic
LANE_UP	out std_logic
WARN_CC	in std_logic
DO_CC	in std_logic
USER_CLK	in std_logic
SYNC_CLK	in std_logic
RESET	in std_logic
POWER_DOWN	in std_logic
LOOPBACK	in std_logic_vector ( 2 downto 0 )
GT_RESET	in std_logic
GTPCLKOUT	out std_logic
RXEQMIX_IN	in std_logic_vector ( 1 downto 0 )
DADDR_IN	in std_logic_vector ( 7 downto 0 )
DCLK_IN	in std_logic
DEN_IN	in std_logic
DI_IN	in std_logic_vector ( 15 downto 0 )
DRDY_OUT	out std_logic
DRPDO_OUT	out std_logic_vector ( 15 downto 0 )
DWE_IN	in std_logic
TX_LOCK	out std_logic

Detailed Description

Definition at line 70 of file klm_aurora.vhd.

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The documentation for this class was generated from the following file:

• klm_aurora/source/klm_aurora.vhd