Belle II KLM Scint Firmware  1
transceiver_wrapper.vhd
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49 --------------------------------------------------------------------------------
50 -- ____ ____
51 -- / /\/ /
52 -- /___/ \ / Vendor: Xilinx
53 -- \ \ \/ Version : 7.1i
54 -- \ \ Application :
55 -- / / Filename : klm_aurora_GTP_WRAPPER.vhd
56 -- /___/ /\ Timestamp : 02/16/2005 10:19:02
57 -- \ \ / \
58 -- \___\/\___\
59 --------------------------------------------------------------------------------
60 --Command:
61 --Design Name: klm_aurora_GTP_WRAPPER
62 --
63 -- Module klm_aurora_GTP_WRAPPER
64 -- Generated by Xilinx Architecture Wizard
65 -- Written for synthesis tool: XST
66 --------------------------------------------------------------------------------
67 library ieee;
68 use ieee.std_logic_1164.ALL;
69 use ieee.numeric_std.ALL;
70 library UNISIM;
71 use UNISIM.Vcomponents.ALL;
72 
73 entity GTP_WRAPPER is
74 generic
75 ( --Simulation attributes
76  SIM_GTPRESET_SPEEDUP : integer := 0; --Set to 1 to speed up sim reset
77  CLK_CORRECT_USE : boolean := TRUE);--Set to true to use clock correction
78 port(
79  ---------------------- Loopback and Powerdown Ports ----------------------
80  LOOPBACK_IN : in std_logic_vector (2 downto 0);
81  --------------------- Receive Ports - 8b10b Decoder ----------------------
82  RXCHARISCOMMA_OUT : out std_logic_vector (1 downto 0);
83  RXCHARISK_OUT : out std_logic_vector (1 downto 0);
84  RXDISPERR_OUT : out std_logic_vector (1 downto 0);
85  RXNOTINTABLE_OUT : out std_logic_vector (1 downto 0);
86  ----------------- Receive Ports - Clock Correction Ports -----------------
87  RXBUFERR_OUT : out std_logic;
88  ------------- Receive Ports - Comma Detection and Alignment --------------
89  RXREALIGN_OUT : out std_logic;
90  ENMCOMMAALIGN_IN : in std_logic;
91  ENPCOMMAALIGN_IN : in std_logic;
92  ----------------- Receive Ports - RX Data Path interface -----------------
93  RXDATA_OUT : out std_logic_vector (15 downto 0);
94  RXRECCLK1_OUT : out std_logic;
95  RXRECCLK2_OUT : out std_logic;
96  RXRESET_IN : in std_logic;
97  RXUSRCLK_IN : in std_logic;
98  RXUSRCLK2_IN : in std_logic;
99  ----- Receive Ports - RX Driver,OOB signalling,Coupling and Eq.,CDR ------
100  RXEQMIX_IN : in std_logic_vector(1 downto 0);
101  RX1N_IN : in std_logic;
102  RX1P_IN : in std_logic;
103  --------------- Receive Ports - RX Polarity Control Ports ----------------
104  RXPOLARITY_IN : in std_logic;
105  ----------- Shared Ports - Dynamic Reconfiguration Port (DRP) ------------
106  DADDR_IN : in std_logic_vector(7 downto 0);
107  DCLK_IN : in std_logic;
108  DEN_IN : in std_logic;
109  DI_IN : in std_logic_vector(15 downto 0);
110  DRDY_OUT : out std_logic;
111  DRPDO_OUT : out std_logic_vector(15 downto 0);
112  DWE_IN : in std_logic;
113  ------------------- Shared Ports - Tile and PLL Ports --------------------
114  REFSELDYPLL : in std_logic_vector(2 downto 0);
115  REFCLK0 : in std_logic;
116  REFCLK1 : in std_logic;
117  GCLK : in std_logic;
118  GTPRESET_IN : in std_logic;
119  PLLLKDET_OUT : out std_logic;
120  -------------- Transmit Ports - 8b10b Encoder Control Ports --------------
121  TXCHARISK_IN : in std_logic_vector (1 downto 0);
122  ---------------- Transmit Ports - TX Data Path interface -----------------
123  TXDATA_IN : in std_logic_vector (15 downto 0);
124  GTPCLKOUT_OUT : out std_logic_vector(1 downto 0);
125  TXRESET_IN : in std_logic;
126  TXUSRCLK_IN : in std_logic;
127  TXUSRCLK2_IN : in std_logic;
128  TXBUFERR_OUT : out std_logic;
129  ------------- Transmit Ports - TX Driver and OOB signalling --------------
130  TX1N_OUT : out std_logic;
131  TX1P_OUT : out std_logic;
132  RXCHARISCOMMA_OUT_unused : out std_logic_vector (1 downto 0);
133  RXCHARISK_OUT_unused : out std_logic_vector (1 downto 0);
134  RXDISPERR_OUT_unused : out std_logic_vector (1 downto 0);
135  RXNOTINTABLE_OUT_unused : out std_logic_vector (1 downto 0);
136  ------------------- Receive Ports - Channel Bonding Ports -----------------
137  RXREALIGN_OUT_unused : out std_logic;
138  RXDATA_OUT_unused : out std_logic_vector (15 downto 0);
139  RX1N_IN_unused : in std_logic;
140  RX1P_IN_unused : in std_logic;
141  RXBUFERR_OUT_unused : out std_logic_vector(2 downto 0);
142  TXBUFERR_OUT_unused : out std_logic_vector(1 downto 0);
143  CHBONDDONE_OUT_unused : out std_logic;
144  TX1N_OUT_unused : out std_logic;
145  TX1P_OUT_unused : out std_logic;
146  POWERDOWN_IN : in std_logic);
147 end GTP_WRAPPER;
148 
149 architecture BEHAVIORAL of GTP_WRAPPER is
150  attribute core_generation_info : string;
151  attribute core_generation_info of BEHAVIORAL : architecture is "klm_aurora,aurora_8b10b_v5_3,{user_interface=Legacy_LL, backchannel_mode=Sidebands, c_aurora_lanes=1, c_column_used=None, c_gt_clock_1=GTPD2, c_gt_clock_2=None, c_gt_loc_1=X, c_gt_loc_10=X, c_gt_loc_11=X, c_gt_loc_12=X, c_gt_loc_13=X, c_gt_loc_14=X, c_gt_loc_15=X, c_gt_loc_16=X, c_gt_loc_17=X, c_gt_loc_18=X, c_gt_loc_19=X, c_gt_loc_2=X, c_gt_loc_20=X, c_gt_loc_21=X, c_gt_loc_22=X, c_gt_loc_23=X, c_gt_loc_24=X, c_gt_loc_25=X, c_gt_loc_26=X, c_gt_loc_27=X, c_gt_loc_28=X, c_gt_loc_29=X, c_gt_loc_3=X, c_gt_loc_30=X, c_gt_loc_31=X, c_gt_loc_32=X, c_gt_loc_33=X, c_gt_loc_34=X, c_gt_loc_35=X, c_gt_loc_36=X, c_gt_loc_37=X, c_gt_loc_38=X, c_gt_loc_39=X, c_gt_loc_4=X, c_gt_loc_40=X, c_gt_loc_41=X, c_gt_loc_42=X, c_gt_loc_43=X, c_gt_loc_44=X, c_gt_loc_45=X, c_gt_loc_46=X, c_gt_loc_47=X, c_gt_loc_48=X, c_gt_loc_5=1, c_gt_loc_6=X, c_gt_loc_7=X, c_gt_loc_8=X, c_gt_loc_9=X, c_lane_width=2, c_line_rate=2.5443, c_nfc=false, c_nfc_mode=IMM, c_refclk_frequency=127.215, c_simplex=false, c_simplex_mode=TX, c_stream=false, c_ufc=false, flow_mode=None, interface_mode=Framing, dataflow_config=Duplex}";
152 --***************************** Compopnent Declaration ****************************
153 component AURORA_TILE is
154 generic(
155  -- Simulation attributes
156  TILE_SIM_GTPRESET_SPEEDUP : integer := 0; -- Set to 1 to speed up sim reset
157  TILE_CLK_CORRECT_USE : boolean := TRUE);--Set to true to use clock correction
158 port(
159  ------------------------ Loopback and Powerdown Ports ----------------------
160  LOOPBACK0_IN : in std_logic_vector(2 downto 0);
161  LOOPBACK1_IN : in std_logic_vector(2 downto 0);
162  RXPOWERDOWN0_IN : in std_logic_vector(1 downto 0);
163  RXPOWERDOWN1_IN : in std_logic_vector(1 downto 0);
164  TXPOWERDOWN0_IN : in std_logic_vector(1 downto 0);
165  TXPOWERDOWN1_IN : in std_logic_vector(1 downto 0);
166  ----------------------- Receive Ports - 8b10b Decoder ----------------------
167  RXCHARISCOMMA0_OUT : out std_logic_vector(1 downto 0);
168  RXCHARISCOMMA1_OUT : out std_logic_vector(1 downto 0);
169  RXCHARISK0_OUT : out std_logic_vector(1 downto 0);
170  RXCHARISK1_OUT : out std_logic_vector(1 downto 0);
171  RXDISPERR0_OUT : out std_logic_vector(1 downto 0);
172  RXDISPERR1_OUT : out std_logic_vector(1 downto 0);
173  RXNOTINTABLE0_OUT : out std_logic_vector(1 downto 0);
174  RXNOTINTABLE1_OUT : out std_logic_vector(1 downto 0);
175  ------------------- Receive Ports - Clock Correction Ports--
176  RXCLKCORCNT0_OUT : out std_logic_vector(2 downto 0);
177  RXCLKCORCNT1_OUT : out std_logic_vector(2 downto 0);
178  --------------- Receive Ports - Comma Detection and Alignment --------------
179  RXBYTEREALIGN0_OUT : out std_logic;
180  RXBYTEREALIGN1_OUT : out std_logic;
181  RXENMCOMMAALIGN0_IN : in std_logic;
182  RXENMCOMMAALIGN1_IN : in std_logic;
183  RXENPCOMMAALIGN0_IN : in std_logic;
184  RXENPCOMMAALIGN1_IN : in std_logic;
185  ------------------- Receive Ports - RX Data Path interface -----------------
186  RXDATA0_OUT : out std_logic_vector(15 downto 0);
187  RXDATA1_OUT : out std_logic_vector(15 downto 0);
188  RXRESET0_IN : in std_logic;
189  RXRESET1_IN : in std_logic;
190  RXUSRCLK0_IN : in std_logic;
191  RXUSRCLK1_IN : in std_logic;
192  RXUSRCLK20_IN : in std_logic;
193  RXUSRCLK21_IN : in std_logic;
194  ------- Receive Ports - RX Driver,OOB signalling,Coupling and Eq.,CDR ------
195  RXEQMIX0_IN : in std_logic_vector(1 downto 0);
196  RXEQMIX1_IN : in std_logic_vector(1 downto 0);
197  RXN0_IN : in std_logic;
198  RXN1_IN : in std_logic;
199  RXP0_IN : in std_logic;
200  RXP1_IN : in std_logic;
201  -------- Receive Ports - RX Elastic Buffer and Phase Alignment Ports -------
202  RXBUFSTATUS0_OUT : out std_logic_vector(2 downto 0);
203  RXBUFSTATUS1_OUT : out std_logic_vector(2 downto 0);
204  TXBUFSTATUS0_OUT : out std_logic_vector(1 downto 0);
205  TXBUFSTATUS1_OUT : out std_logic_vector(1 downto 0);
206  ----------------- Receive Ports - RX Polarity Control Ports ----------------
207  RXPOLARITY0_IN : in std_logic;
208  RXPOLARITY1_IN : in std_logic;
209  ------------- Shared Ports - Dynamic Reconfiguration Port (DRP) ------------
210  DADDR_IN : in std_logic_vector(7 downto 0);
211  DCLK_IN : in std_logic;
212  DEN_IN : in std_logic;
213  DI_IN : in std_logic_vector(15 downto 0);
214  DRDY_OUT : out std_logic;
215  DRPDO_OUT : out std_logic_vector(15 downto 0);
216  DWE_IN : in std_logic;
217  --------------------- Shared Ports - Tile and PLL Ports --------------------
218  REFSELDYPLL0_IN : in std_logic_vector(2 downto 0);
219  REFSELDYPLL1_IN : in std_logic_vector(2 downto 0);
220  CLK00_IN : in std_logic;
221  CLK01_IN : in std_logic;
222  CLK10_IN : in std_logic;
223  CLK11_IN : in std_logic;
224  GCLK00_IN : in std_logic;
225  GCLK01_IN : in std_logic;
226  GCLK10_IN : in std_logic;
227  GCLK11_IN : in std_logic;
228  GTPRESET0_IN : in std_logic;
229  GTPRESET1_IN : in std_logic;
230  PLLLKDET0_OUT : out std_logic;
231  PLLLKDET1_OUT : out std_logic;
232  RESETDONE0_OUT : out std_logic;
233  RESETDONE1_OUT : out std_logic;
234  ---------------- Transmit Ports - 8b10b Encoder Control Ports --------------
235  TXCHARISK0_IN : in std_logic_vector(1 downto 0);
236  TXCHARISK1_IN : in std_logic_vector(1 downto 0);
237  -------------- Transmit Ports - 64b66b and 64b67b Gearbox Ports ------------
238  TXDATA0_IN : in std_logic_vector(15 downto 0);
239  TXDATA1_IN : in std_logic_vector(15 downto 0);
240  GTPCLKOUT0_OUT : out std_logic_vector(1 downto 0);
241  GTPCLKOUT1_OUT : out std_logic_vector(1 downto 0);
242  TXRESET0_IN : in std_logic;
243  TXRESET1_IN : in std_logic;
244  TXUSRCLK0_IN : in std_logic;
245  TXUSRCLK1_IN : in std_logic;
246  TXUSRCLK20_IN : in std_logic;
247  TXUSRCLK21_IN : in std_logic;
248  --------------- Transmit Ports - TX Driver and OOB signalling --------------
249  TXN0_OUT : out std_logic;
250  TXN1_OUT : out std_logic;
251  TXP0_OUT : out std_logic;
252  TXP1_OUT : out std_logic);
253 end component;
254 
255  signal tied_to_ground_i : std_logic;
256  signal tied_to_ground_vec_i : std_logic_vector (63 downto 0);
257 
258  signal open_rxbufstatus : std_logic_vector (1 downto 0);
259  signal open_txbufstatus : std_logic;
260  signal open_rxbufstatus_lane1 : std_logic_vector (1 downto 0);
261  signal open_txbufstatus_lane1 : std_logic;
262  --signal to output lock signal
263  signal plllkdet_i : std_logic;
264  signal plllkdet_lane1_i : std_logic;
265 
266  signal resetdone0_i : std_logic;
267  signal resetdone1_i : std_logic;
268 
269 begin
270 
271  tied_to_ground_i <= '0';
272  tied_to_ground_vec_i(63 downto 0) <= x"0000000000000000";
273 
274 
275 --Assign lock signals
276  PLLLKDET_OUT <= plllkdet_i;
277 
278 --*************************************************************************************************
279 -------------------------------------EVEN GTP-----------------------------------------------
280 --*************************************************************************************************
281  GTP_TILE_INST : AURORA_TILE
282  generic map(
283  --_______________________ Simulation-Only Attributes __________________
284  TILE_SIM_GTPRESET_SPEEDUP => SIM_GTPRESET_SPEEDUP,
285  TILE_CLK_CORRECT_USE => CLK_CORRECT_USE)
286  port map(
287  ------------------------ Loopback and Powerdown Ports ----------------------
288  LOOPBACK0_IN => LOOPBACK_IN,
289  LOOPBACK1_IN => "000",
290  RXPOWERDOWN0_IN(0) => POWERDOWN_IN,
291  RXPOWERDOWN0_IN(1) => POWERDOWN_IN,
292  RXPOWERDOWN1_IN(1 downto 0) => tied_to_ground_vec_i(1 downto 0),
293  TXPOWERDOWN0_IN(0) => POWERDOWN_IN,
294  TXPOWERDOWN0_IN(1) => POWERDOWN_IN,
295  TXPOWERDOWN1_IN(1 downto 0) => tied_to_ground_vec_i(1 downto 0),
296  ----------------------- Receive Ports - 8b10b Decoder ----------------------
297  RXCHARISCOMMA0_OUT => RXCHARISCOMMA_OUT ,
298  RXCHARISCOMMA1_OUT => RXCHARISCOMMA_OUT_unused,
299  RXCHARISK0_OUT => RXCHARISK_OUT,
300  RXCHARISK1_OUT => RXCHARISK_OUT_unused,
301  RXDISPERR0_OUT => RXDISPERR_OUT,
302  RXDISPERR1_OUT => RXDISPERR_OUT_unused,
303  RXNOTINTABLE0_OUT => RXNOTINTABLE_OUT,
304  RXNOTINTABLE1_OUT => RXNOTINTABLE_OUT_unused,
305  ------------------- Receive Ports - Channel Bonding Ports ------------------
306  ------------------- Receive Ports - Clock Correction Ports -----------------
307  RXCLKCORCNT0_OUT => open,
308  RXCLKCORCNT1_OUT => open,
309  --------------- Receive Ports - Comma Detection and Alignment --------------
310  RXBYTEREALIGN0_OUT => RXREALIGN_OUT ,
311  RXBYTEREALIGN1_OUT => RXREALIGN_OUT_unused,
312  RXENMCOMMAALIGN0_IN => ENMCOMMAALIGN_IN,
313  RXENMCOMMAALIGN1_IN => tied_to_ground_i,
314  RXENPCOMMAALIGN0_IN => ENPCOMMAALIGN_IN,
315  RXENPCOMMAALIGN1_IN => tied_to_ground_i,
316  ------------------- Receive Ports - RX Data Path interface -----------------
317  RXDATA0_OUT => RXDATA_OUT,
318  RXDATA1_OUT => RXDATA_OUT_unused,
319  RXRESET0_IN => RXRESET_IN ,
320  RXRESET1_IN => tied_to_ground_i,
321  RXUSRCLK0_IN => RXUSRCLK_IN,
322  RXUSRCLK1_IN => tied_to_ground_i ,
323  RXUSRCLK20_IN => RXUSRCLK2_IN,
324  RXUSRCLK21_IN => tied_to_ground_i,
325  ------- Receive Ports - RX Driver,OOB signalling,Coupling and Eq.,CDR ------
326  RXEQMIX0_IN => RXEQMIX_IN,
327  RXEQMIX1_IN => "00",
328  RXN0_IN => RX1N_IN,
329  RXN1_IN => RX1N_IN_unused,
330  RXP0_IN => RX1P_IN,
331  RXP1_IN => RX1P_IN_unused,
332  -------- Receive Ports - RX Elastic Buffer and Phase Alignment Ports -------
333  RXBUFSTATUS0_OUT(2) => RXBUFERR_OUT ,
334  RXBUFSTATUS0_OUT(1 downto 0) => open_rxbufstatus(1 downto 0),
335  RXBUFSTATUS1_OUT => RXBUFERR_OUT_unused,
336  TXBUFSTATUS0_OUT(1) => TXBUFERR_OUT ,
337  TXBUFSTATUS0_OUT(0) => open_txbufstatus,
338  TXBUFSTATUS1_OUT => TXBUFERR_OUT_unused,
339  ----------------- Receive Ports - RX Polarity Control Ports ----------------
340  RXPOLARITY0_IN => RXPOLARITY_IN,
341  RXPOLARITY1_IN => tied_to_ground_i,
342  ------------- Shared Ports - Dynamic Reconfiguration Port (DRP) ------------
343  DADDR_IN => DADDR_IN,
344  DCLK_IN => DCLK_IN,
345  DEN_IN => DEN_IN,
346  DI_IN => DI_IN,
347  DRDY_OUT => DRDY_OUT,
348  DRPDO_OUT => DRPDO_OUT,
349  DWE_IN => DWE_IN,
350  --------------------- Shared Ports - Tile and PLL Ports --------------------
351  REFSELDYPLL0_IN => REFSELDYPLL,
352  REFSELDYPLL1_IN => REFSELDYPLL,
353  CLK00_IN => REFCLK0,
354  CLK01_IN => REFCLK0,
355  CLK10_IN => REFCLK1,
356  CLK11_IN => REFCLK1,
357  GCLK00_IN => GCLK,
358  GCLK01_IN => GCLK,
359  GCLK10_IN => GCLK,
360  GCLK11_IN => GCLK,
361  GTPRESET0_IN => GTPRESET_IN,
362  GTPRESET1_IN => GTPRESET_IN,
363  PLLLKDET0_OUT => plllkdet_i,
364  PLLLKDET1_OUT => plllkdet_lane1_i,
365  RESETDONE0_OUT => resetdone0_i,
366  RESETDONE1_OUT => resetdone1_i,
367  ---------------- Transmit Ports - 8b10b Encoder Control Ports --------------
368  TXCHARISK0_IN => TXCHARISK_IN,
369  TXCHARISK1_IN => tied_to_ground_vec_i(1 downto 0),
370  ------------------ Transmit Ports - TX Data Path interface -----------------
371  TXDATA0_IN => TXDATA_IN,
372  TXDATA1_IN => tied_to_ground_vec_i(15 downto 0),
373  GTPCLKOUT0_OUT => GTPCLKOUT_OUT,
374  GTPCLKOUT1_OUT => open,
375  TXRESET0_IN => TXRESET_IN ,
376  TXRESET1_IN => tied_to_ground_i,
377  TXUSRCLK0_IN => TXUSRCLK_IN,
378  TXUSRCLK1_IN => tied_to_ground_i,
379  TXUSRCLK20_IN => TXUSRCLK2_IN,
380  TXUSRCLK21_IN => tied_to_ground_i,
381  --------------- Transmit Ports - TX Driver and OOB signalling --------------
382  TXN0_OUT => TX1N_OUT,
383  TXN1_OUT => TX1N_OUT_unused,
384  TXP0_OUT => TX1P_OUT,
385  TXP1_OUT => TX1P_OUT_unused
386  );
387 end BEHAVIORAL;
AURORA_TILE
Definition: aurora_tile.vhd:73
GTP_WRAPPER
Definition: transceiver_wrapper.vhd:73