CREAM TEA Readout Project

TARGET2 floorplan

Design Reference Page

All information tentative and provided for informational reasons.

No recent updates -- archival at this point (TARGET6 probably desired ASIC).

Thoughts about a Rev. B readout version that exploits eKLM/iTOP beam/cosmic test infrastructure:   [PDF]
16 JAN 2011 links to most recent CREAMTEA versions:
  1. Software:  [link]
  2. Firmware:  [link]

15 JUL 2010 archival snapshots (pre serious debug):
  1. MCP_MAINv02  [ZIP archive]
  2. MCP_TARGETv04  [ZIP archive]
  3. MCP_TARGET_BOTTOMv01  [ZIP archive]
  4. FIN_CLKv01  [ZIP archive]
And some specific monitor header signal documentation PDFs:
  1. FIN_CLK items
    1. TOP sheet  [PDF]
    2. TARGET_IF  [PDF]
    1. TOP sheet  [PDF]
  3. MCP_TARGETv04
    1. TOP sheet  [PDF]

Previous archive of working items for readout:
  1. Ryan's software link [webpage]
  2. Current readout module schematics
    1. Zip [archive] for hardware boards (main, TARGET, cPCI)
    2. Zip [archive] for current firmware [16-APR-2010] for boards given to Ryan
    3. MCP_main board (Larry) [PDF schematics]
    4. MCP_TARGET board (Larry) [PDF schematics]
    5. MCP_TARGET_BOTTOM board (Larry) [PDF schematics]
    6. MCP_cPCI board (Larry) [PDF schematics]
    7. M64 interface/diode protection board (Jim) [PDF]  [PADS schematics]
  3. Current list of action items: [TBI]
  4. Archival information:
    1. Baseline firmware, Dec 2009 (ISE v10.3) [firmware]

The initial CREAM TEA readout is based upon the first generation TARGET ASIC and TARGET (v1) Reference Documents (many related to TARGET_Eval board):
  1. Reference documents from 19-MAR-2010 conversation with Leonid:
    1. Estimated sampling rate from RCO scaling [xls]
    2. Reference sampling rate measurement using TSA [xls]
  2. TARGET data sheet  [PDF]
  3. Andrew Wong's [software page] which includes:
    1. Oct. 6, 2008 [software release]
    2. Sept. 24, 2008 (Rev. C) [firmware release]
    3. Aug. 27, 2007 [documentation release] 
  4. Larry's MCP_main Eval board design (Rev. C) [schematics]
  5. Latest (fairly old -- v.3) paper draft [PDF] [tex source] 
  6. Testing (as of paper v3) action items [list]

Testing reference list for paper:

Table 1: TARGET design specs
Number of channels
better density (BLAB3/IRS = 8 ch)
Storage cells/channel
8 x groups of 512 samples
Sampling rate
0.5 - 2.5
Dynamic range
bits (effective); 12-bits recordable
x Voltage (-3dB at 180MHz) for 100 Ohm termination
Wilkinson ADC clock speed
~100 MHz (inside FPGA)
ADC conversion
2 x 16
Convert same group 16 from 2 channels (in top/bottom 8) in parallel
Readout time/sample
ns   (random accessing with 64 samples and 16 channels)
Trigger outputs
1 + 1
1 digital OR of 8 channels, 1 analog (pull-down) sum

[UH Physics] [University of Hawaii]
Last modified: 1/13/2013