Item
|
Value
|
Unit/comment
|
Number of channels
|
16
|
better density (BLAB3/IRS = 8
ch)
|
Storage cells/channel
|
4096
|
8 x groups of 512 samples
|
Sampling rate
|
0.5 - 2.5
|
Giga-samples/s
|
Dynamic range
|
9
|
bits (effective); 12-bits
recordable
|
Gain
|
1
|
x Voltage (-3dB at 180MHz)
for
100 Ohm termination
|
Wilkinson ADC clock speed
|
~100 |
MHz (inside FPGA)
|
ADC conversion
|
2 x 16
|
Convert same group 16 from 2
channels (in top/bottom 8) in parallel
|
Readout time/sample
|
20
|
ns (random
accessing
with 64 samples and 16 channels)
|
Trigger outputs
|
1 + 1
|
1 digital OR of 8 channels, 1
analog (pull-down) sum
|