MCP_MAINv01 Project Status
Project File: MCP_MAINv01.ise Current State: Programming File Generated
Module Name: TOP
  • Errors:
No Errors
Target Device: xc2vp2-5fg256
  • Warnings:
264 Warnings
Product Version: ISE 10.1.03 - Foundation Simulator
  • Routing Results:
All Signals Completely Routed
Design Goal: Balanced
  • Timing Constraints:
All Constraints Met
Design Strategy: Xilinx Default (unlocked)
  • Final Timing Score:
(Timing Report)
 
MCP_MAINv01 Partition Summary [-]
No partition information was found.
 
Device Utilization Summary [-]
Logic UtilizationUsedAvailableUtilizationNote(s)
Number of Slice Flip Flops 651 2,816 23%  
Number of 4 input LUTs 775 2,816 27%  
Logic Distribution     
Number of occupied Slices 699 1,408 49%  
    Number of Slices containing only related logic 699 699 100%  
    Number of Slices containing unrelated logic 0 699 0%  
Total Number of 4 input LUTs 958 2,816 34%  
    Number used as logic 775      
    Number used as a route-thru 183      
Number of bonded IOBs
Number of bonded 109 140 77%  
    IOB Master Pads 14      
    IOB Slave Pads 14      
Number of BUFGMUXs 7 16 43%  
Number of DCMs 1 4 25%  
Number of GTs 1 4 25%  
Number of RPM macros 2      
 
Performance Summary [-]
Final Timing Score: 0 Pinout Data: Pinout Report
Routing Results: All Signals Completely Routed Clock Data: Clock Report
Timing Constraints: All Constraints Met    
 
Detailed Reports [-]
Report NameStatusGenerated ErrorsWarningsInfos
Synthesis ReportCurrentTue Apr 13 15:01:55 20100244 Warnings37 Infos
Translation ReportCurrentTue Apr 13 15:02:03 201001 Warning0
Map ReportCurrentTue Apr 13 15:02:11 2010017 Warnings7 Infos
Place and Route ReportCurrentTue Apr 13 15:02:30 201002 Warnings1 Info
Static Timing ReportCurrentTue Apr 13 15:02:35 201001 Warning2 Infos
Bitgen ReportCurrentTue Apr 13 15:02:45 201002 Warnings1 Info

Date Generated: 04/14/2010 - 12:54:41