MCP_TARGETv01 Project Status (04/14/2010 - 16:10:24)
Project File: MCP_TARGETv01.ise Current State: Programming File Generated
Module Name: TOP
  • Errors:
No Errors
Target Device: xc3s400-4pq208
  • Warnings:
390 Warnings
Product Version: ISE 10.1.03 - Foundation Simulator
  • Routing Results:
All Signals Completely Routed
Design Goal: Balanced
  • Timing Constraints:
X 1 Failing Constraint
Design Strategy: Xilinx Default (unlocked)
  • Final Timing Score:
5840 (Timing Report)
 
MCP_TARGETv01 Partition Summary [-]
No partition information was found.
 
Device Utilization Summary [-]
Logic UtilizationUsedAvailableUtilizationNote(s)
Number of Slice Flip Flops 1,456 7,168 20%  
Number of 4 input LUTs 3,953 7,168 55%  
Logic Distribution     
Number of occupied Slices 2,893 3,584 80%  
    Number of Slices containing only related logic 2,893 2,893 100%  
    Number of Slices containing unrelated logic 0 2,893 0%  
Total Number of 4 input LUTs 4,282 7,168 59%  
    Number used as logic 3,933      
    Number used as a route-thru 329      
    Number used as Shift registers 20      
Number of bonded IOBs
Number of bonded 111 141 78%  
    IOB Master Pads 4      
    IOB Slave Pads 4      
Number of RAMB16s 3 16 18%  
Number of BUFGMUXs 6 8 75%  
Number of DCMs 1 4 25%  
Number of RPM macros 2      
 
Performance Summary [-]
Final Timing Score: 5840 Pinout Data: Pinout Report
Routing Results: All Signals Completely Routed Clock Data: Clock Report
Timing Constraints: X 1 Failing Constraint    
 
Detailed Reports [-]
Report NameStatusGenerated ErrorsWarningsInfos
Synthesis ReportCurrentWed Apr 14 16:09:25 20100371 Warnings35 Infos
Translation ReportCurrentWed Apr 14 16:09:35 201001 Warning1 Info
Map ReportCurrentWed Apr 14 16:09:45 201008 Warnings3 Infos
Place and Route ReportCurrentWed Apr 14 16:10:09 2010010 Warnings0
Static Timing ReportCurrentWed Apr 14 16:10:14 2010002 Infos
Bitgen ReportCurrentWed Apr 14 16:10:23 2010002 Infos

Date Generated: 04/14/2010 - 16:10:24