MCP_cPCIv21 Project Status
Project File: MCP_cPCIv21.ise Current State: Programming File Generated
Module Name: TOP
  • Errors:
No Errors
Target Device: xc2vp20-5ff1152
  • Warnings:
480 Warnings
Product Version: ISE 10.1.03 - Foundation Simulator
  • Routing Results:
All Signals Completely Routed
Design Goal: Balanced
  • Timing Constraints:
All Constraints Met
Design Strategy: Xilinx Default (unlocked)
  • Final Timing Score:
(Timing Report)
 
MCP_cPCIv21 Partition Summary [-]
Partition NameSynthesis StatusPlacement StatusRouting Status
/TOP Implemented ImplementedImplemented
/TOP/pciguest/bridge Preserved PreservedPreserved
 
Device Utilization Summary [-]
Logic UtilizationUsedAvailableUtilizationNote(s)
Number of Slice Flip Flops 4,130 18,560 22%  
Number of 4 input LUTs 4,786 18,560 25%  
Logic Distribution     
Number of occupied Slices 4,030 9,280 43%  
    Number of Slices containing only related logic 4,030 4,030 100%  
    Number of Slices containing unrelated logic 0 4,030 0%  
Total Number of 4 input LUTs 5,660 18,560 30%  
    Number used as logic 4,786      
    Number used as a route-thru 874      
Number of bonded IOBs
Number of bonded 401 564 71%  
Number of RAMB16s 20 88 22%  
Number of BUFGMUXs 15 16 93%  
Number of DCMs 5 8 62%  
Number of GTs 8 8 100%  
 
Performance Summary [-]
Final Timing Score: 0 Pinout Data: Pinout Report
Routing Results: All Signals Completely Routed Clock Data: Clock Report
Timing Constraints: All Constraints Met    
 
Detailed Reports [-]
Report NameStatusGenerated ErrorsWarningsInfos
Synthesis ReportCurrentMon Mar 23 06:13:28 20090379 Warnings7 Infos
Translation ReportCurrentMon Mar 23 06:13:46 2009010 Warnings9 Infos
Map ReportCurrentMon Mar 23 06:14:18 2009087 Warnings5 Infos
Place and Route ReportCurrentMon Mar 23 06:15:42 200904 Warnings1 Info
Static Timing ReportCurrentMon Mar 23 06:15:56 2009002 Infos
Bitgen ReportCurrentMon Mar 23 06:16:20 2009052 Warnings1 Info

Date Generated: 04/16/2010 - 10:05:54