MCP_TARGET_BOTTOMv01 Project Status (04/13/2010 - 14:53:13)
Project File: MCP_TARGET_BOTTOMv01.ise Current State: Programming File Generated
Module Name: TOP
  • Errors:
No Errors
Target Device: xc3s400-4pq208
  • Warnings:
38 Warnings
Product Version: ISE 10.1.03 - Foundation Simulator
  • Routing Results:
All Signals Completely Routed
Design Goal: Balanced
  • Timing Constraints:
All Constraints Met
Design Strategy: Xilinx Default (unlocked)
  • Final Timing Score:
(Timing Report)
 
MCP_TARGET_BOTTOMv01 Partition Summary [-]
No partition information was found.
 
Device Utilization Summary [-]
Logic UtilizationUsedAvailableUtilizationNote(s)
Number of Slice Flip Flops 327 7,168 4%  
Number of 4 input LUTs 335 7,168 4%  
Logic Distribution     
Number of occupied Slices 335 3,584 9%  
    Number of Slices containing only related logic 335 335 100%  
    Number of Slices containing unrelated logic 0 335 0%  
Total Number of 4 input LUTs 418 7,168 5%  
    Number used as logic 260      
    Number used as a route-thru 83      
    Number used as Shift registers 75      
Number of bonded IOBs
Number of bonded 29 141 20%  
    IOB Master Pads 11      
    IOB Slave Pads 11      
Number of RAMB16s 3 16 18%  
Number of BUFGMUXs 3 8 37%  
Number of BSCANs 1 1 100%  
Number of RPM macros 14      
 
Performance Summary [-]
Final Timing Score: 0 Pinout Data: Pinout Report
Routing Results: All Signals Completely Routed Clock Data: Clock Report
Timing Constraints: All Constraints Met    
 
Detailed Reports [-]
Report NameStatusGenerated ErrorsWarningsInfos
Synthesis ReportCurrentTue Apr 13 14:52:46 2010018 Warnings2 Infos
Translation ReportCurrentTue Apr 13 14:52:52 2010000
Map ReportCurrentTue Apr 13 14:52:56 2010014 Warnings2 Infos
Place and Route ReportCurrentTue Apr 13 14:53:05 201006 Warnings1 Info
Static Timing ReportCurrentTue Apr 13 14:53:08 201001 Warning2 Infos
Bitgen ReportCurrentTue Apr 13 14:53:12 201001 Warning1 Info

Date Generated: 04/13/2010 - 14:53:13