DUNE
Cold Electronics in Hawaii
Jeff Kleyner, Ethan Lee, Kurtis
Nishimura, Gary Varner
Most Recent - Rev B:
Finalized files: 3/3/2021
Layout
- [pdf]
- [zip]
- [pcb]
Schematic - [pdf] - [zip]
Gerbers - [zip]
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almost there files:
Layout - [pdf]
- [zip]
Schematic - [pdf] - [zip]
Gerbers - [zip]
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3/2/21
Layout - [pdf]
- [zip]
Schematic - [pdf] - [zip]
Gerbers - [zip]
----------------------------------------------------------------------------------------------
2/27/21
project [zip]
-all digital routing done,
-all vias dropped
-pours checked, seems ok (addressed comments from Kurtis)
--added more vias after
though, so need to recheck
-addressed previous comments from review
Need to do:
route debug connectors
route testpoint connectors
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2/24/21
Layout - [pads]
(oops, its a zip)
Project folder - [zip]
New design, without 1V 2V LDOs external. A lot more caps, many
100uF 1210 pkg size
Notes from today's SLAC meeting review:
- SMA
connections --> 2 pin jumpers
- layer names in
stack (now that things have changed)
- add gnd pins
to debug connector and testpoint connector
- tie analog to
digital gnd by the connector or center of board. Can just
have additional footprints and load what we want
- sense
resistors at connector for analog raw power, instead of
regulated 2.5
- install buffer
resistors on the bottom layer, underneath lvds drivers.
makes diff pair traces better
- AC couple the
drivers to the ASICs, 0.1uF caps 0603 small pkg
- route digital
gnd planes around asic and analog ldo planes. currently
acting as a capacitor with only silicon between layers 5
& 6
- adjust net
colors to distinguish Ana and Dig
- schematic:
adjust text as its hard to read some things (export messes
up text placement)
- schematic: add
component properties and tolerances, instead of just on
BOM
Need to finish tomorrow/friday. Fab starting on Monday =
getting boards to ICEBERG by 3/15
__________________________________________________________________________________________________
1/27/2021
Layout - [zip]
Schem - [zip]
new net: diode_plane
used to load either VSS or analog DC V in (net FE_ANA_IN) to
pin 2 of all of the protection diodes. The plane has a choke
point and a mounting hole in the way, needs to be addressed.
also need to swap pin 2 vias from vss to diode_plane
added two 10-pin connectors for debugging connections. they
need to be 12 pin however to accommodate all cryo options
currently? will check and confirm.
routing: working on SACI connections, data, debug
add 4 more test points, one per bank of asics (L_top,
L_bottom, R_top, R_bottom) for internal ldo outputs
double checked all caps, compared to slac and bnl for cold
capabilities
__________________________________________________________________________________________________
12/30/20
Gerbers - [zip]
Layout - [zip]
Schem - [zip]
This progress is for acquiring a quote for
fab. Majority of routing is complete, vias, thinnest traces,
etc.
Still need to:
-Missing SACI and data
connections from ASICs to Samtec data connector
-connect and label test
points
-confirm X,Y coordinates
of bottom 3 mounting holes, check with BNL file
-add cutout/hole for
posts for data cable, compare to mezzanine pdf
-clean up some vias to
make the pours nicer, a few bad thermals, some via walls
__________________________________________________________________________________________________
Above is Revision B
Below is Revision A
__________________________________________________________________________________________________
Most Recent version: 5/17
Layout - [zip]
Schematic - [zip]
Schematic - [pdf]
Gerbers
- [zip]
Schematic [5/21] - [zip] - trying to make
BOM
__________________________________________________________________________________________________
5/15
Layout - [zip]
Schematic - [zip]
Schematic - [pdf]
Gerbers
- [zip]
-Still need to do remaining diff
pairs, and fix lvds drivers up top
__________________________________________________________________________________________________
5/13
Layout - [zip]
-finished bottom layer of left side.
wont take long to copy the bottom right side to be the
same [ill do thursday]
-left BNL notes on the side but can
delete them. Saw info there that wasnt repeated and
wanted to double check
-need to route couple clusters of
testing components using analog signal layer [i can
finish thursday]
-need to route digital signals from
cryo to connector using digital signal layer [i can try
but would like help as diff pair lines, clks, etc, need
to route correctly. also might need to change high speed
routing rules?]
-need to place refdes on silkscreen
[quickly on zoom?]
-need to mark DNI for BOM [I can go
through quick]
-done?
__________________________________________________________________________________________________
5/11
Layout - [zip]
power routed everywhere
need to route asics and digital signals
and test points
__________________________________________________________________________________________________
5/10
Layout - [zip]
Schem - [zip]
-re designed LDO placement for routing. New planes for intermediary
routing steps.
- havent dropped the vias and
connected it yet but will do so first thing monday.
-need to route the TPs/contact
points/0ohmR
__________________________________________________________________________________________________
Most Recent version: 5/7
Layout - [zip]
Schematic - [zip]
__________________________________________________________________________________________________
5/5/20
Layout - [zip]
Schematic - [zip]
__________________________________________________________________________________________________
5/4/20
Layout - [zip]
-good save file, current has
corrupted issues with some nets, might need to restart from this
point [fatal database error 2015]
-planes relabled, re
layered, nets + color coded
__________________________________________________________________________________________________
5/3/20
Layout - [zip]
-planes
and power everywhere.
-bad
planes labeled -trash
-need to
delete bad planes and order everything as they are numbered.
(order: top, A pwr, signal, A gnd, D gnd, signal, D pwr, bottom)
-can gnd
planes be entire board as drawn?
-currently doing the traces and completing the rest of the routing
__________________________________________________________________________________________________
5/2/20
Layout
- [zip]
Schematic - [zip]
-Pre
routing save
-tomorrow will finish routing and will send.
-Aiming
to review Monday, post IDL meeting ~2pm HST
__________________________________________________________________________________________________
4/30/20
Layout - [zip]
__________________________________________________________________________________________________
4/29/20
Layout - [zip]
Schematic- [zip]
-need to adjust cryo
components
....routing
__________________________________________________________________________________________________
4/28/20
Layout - [zip]
power
layout placement. finishing cryo caps and res. now need to route
and adjust as needed
__________________________________________________________________________________________________
4/26/20
Layout
- [zip]
grouped by circuits. placing
them in respective locations within the board dimensions
__________________________________________________________________________________________________
4/19/20
Layout
- [zip]
will bring up all questions
and comments in meeting
- redoing analog
inputs to satisfy proximity error
-proper order of planes. sandwich routes
between power/gnd
-two planes are connections of chip out to capacitors
-maybe not enough space for all the caps, so change layer so that
caps
can sit above and below?
-are the planes made right, as far as big border, and it changes
within the smaller cutouts? maybe need to define inner shapes as
cutouts?
__________________________________________________________________________________________________
4/10/20
Layout
- [zip]
Schematic - [zip]
- flipped planes
(180)
- associated nets to
planes
- unnamed nets are used to
connect via vias
- need review of planes.
- already know: shift planes
slightly, things are not symmetrical nor centered, extend power/gnd
up to cover entire board
__________________________________________________________________________________________________
3/26/20
Layout
- [zip]
- was able to get the layers
reshaped to fit within the board dimensions
- having an issue with moving the
asics up to the new spot based on the layers. the routes reattach
to what they want.
_______________________________________________________________________________________________________
fanout for routing and planes. Need to
position planes and tie them into the proper nets/pours
Schematic - [zip]
Layout - [zip]
_______________________________________________________________________________________________________
1/22/20
Swapped VSS and VSS_D on cryo
LDO filtering. They were inversed
Schematic - [zip]
Schematic - [pdf]
Layout - [zip]
_______________________________________________________________________________________________________
1/15/20
Schematic - [zip]
Schematic - [pdf]
Layout - [zip]
_______________________________________________________________________________________________________
1/10/20
Schematic - [zip]
Schematic - [pdf]
Layout - [zip]
Currently working version.
Should still rename input pins to 0-63_l and 0-63_r across:
Input connection, protection diodes, input capacitors/filtering
_______________________________________________________________________________________________________
Designer schematic [zip]
-needs renumbering of input channels:
we upgraded from 4 sets of 16 to one asic
running 64 pins.
would be good to have everything reordered
0-63_l and 0-63_r
-fixed the issue of cryo symbol having pins 128-240ish as being
inversed ( right and top sides)
but issue with nets flipping and reconnecting.
need to reconnect top and right sides of both
cryos with the correct net to pin
SLAC comments:
- Split monitor signals, currently in parallel
- CRYO nEXO / v0.2, clock names changed
- otherwise only 4pins changed
- change subscripts to _L and _R for easier reading
- inputs (0-15 * 4) to (0-63 * 2)
- change jumpers to 0 ohm R, physical weak point in cold
environment
- LDOs spec sheet only shows 20pins. brookh used schematic symb
with 29/30 pins? what does the layout footprint have
- I recall the layout is 5 pins on each side, will confirm
- which schematic pins are multiple and why?
_______________________________________________________________________________________________________
Previous uploads:
PADS schematic pdf test
(20-SEPTEMBER-2019) [pdf]
PADS schematic pdf 1st draft
(1-OCTOBER-2019) [pdf]
PADS schematic pdf 2nd draft
(2-OCTOBER-2019) [pdf]
PADS schematic pdf 3rd draft
(2-OCTOBER-2019) [pdf]
PADS schematic pdf 4th draft
with REFDES (4-OCTOBER-2019) [pdf]
PADS schematic pdf 5th draft post
local-review edits (8-OCTOBER-2019) [pdf]
PADS schematic 5th draft PADS
DESIGNER [zip]
12/30 Designer
schematic [zip]
cryo_sch_zip_12_30
Starting Material:
- CRYO WIB Mods #2 (24-JAN-2019) [pdf]
- CRYO FEMB (from July 2018 BNL CE WS) [pptx]
- CRYO wire-bond (Dionisio) [16-JAN-2019]
- PADS Layout (21-FEB-2019) [sch]
- PADS Designer (21-FEB-2019) [zip]
- CRYO pinlist [ods]
- CRYO pinlist for footprint [ods]
PDFs
- Placed cryos on pcb. Currently cleaning up remaining layers.
Analog inputs on chips are connected. Connecting power to
correct planes
- PADS Layout (21-MAY-2019) [zip]
- PADS Designer (21-MAY-2019) [zip]
- PADS Layout (25-JULY-2019) [zip]
- PADS Designer (25-JULY-2019) [zip]
- PADS Layout (30-AUGUST-2019) [zip]
- PADS Designer (30-AUGUST-2019) [zip]
- missing aux input still for testing
- jumper for intput LDOs
[UH Physics] [University of Hawaii]
Last modified:
1/15/2020
-- JK
