Behavioral Architecture Reference

Processes
SC_buffering	( clk , fifos_empty , all_fifos_empty )
fifo_rst_fan5	( clk , fifo_rst )
fifo_rst_fan3	( clk , fifo_rst_r1 )
rst_buff	( clk , rst )
ped_fifo_ch_mux	( clk , ped_fifo_wr_ena , ped_fifo_wr_chan , ped_fifo_din )
wave_fifo_ch_wr	( clk , wave_fifo )
ch_mask_proc	( clk , new_mask_q0 , disambig_tb5 , chan_mask , tb5arr )
fifo_dout_buff	( clk , fifo_dout_q0 , fifos_valid_q0 )
fifo_rd_mux	( clk , fifo_chan_sel , fifo_dout_q1 , fifos_valid_q1 )
dsp_ena_buff	( clk , ena , dig_store_proc_ena )
dsp_FSM	( clk , dig_store_proc_ena , asic_mask , digNshift_ena , digNshift_busy )

Constants
WAVE_DIN_BUFF_DEPTH	integer := 3
wave_fifo_din_t0	wave_fifo_din_t := ( wr_ena = > ( others = > ' 0 ' ) , din = > ( others = > ( others = > ' 0 ' ) ) )

Types
buff_wave_fifo_din_t	( WAVE_DIN_BUFF_DEPTH- 1 downto 0 ) wave_fifo_din_t
SingleBusProcessing_machine	( IDLE , WAIT_DIG_N_SHIFT )

Signals
all_fifos_empty	std_logic_vector ( SLOW_CTRL_BUFF downto 0 )
fifo_rst_r1	std_logic_vector ( 4 downto 0 ) := ( others = > ' 0 ' )
fifo_rst_r2	std_logic_vector ( 14 downto 0 ) := ( others = > ' 0 ' )
proc_reset	std_logic := ' 0 '
ped_fifo_wr_ena_q1	std_logic_vector ( 14 downto 0 ) := ( others = > ' 0 ' )
ped_fifo_wr_ena_q2	std_logic_vector ( 14 downto 0 ) := ( others = > ' 0 ' )
ped_fifo_din_q1	std_logic_vector ( 11 downto 0 ) := ( others = > ' 0 ' )
ped_fifo_din_q2	std_logic_vector ( 11 downto 0 ) := ( others = > ' 0 ' )
wave_fifo	buff_wave_fifo_din_t := ( others = > wave_fifo_din_t0 )
new_mask_q1	slv15 ( 4 downto 0 ) := ( others = > " 000000000000000 " )
fifo_dout_q1	slv24 ( 14 downto 0 ) := ( others = > ( others = > ' 0 ' ) )
fifos_valid_q1	std_logic := ' 0 '
fifo_rd_ena_q1	std_logic_vector ( 14 downto 0 ) := ( others = > ' 0 ' )
fifos_valid_q2	std_logic := ' 0 '
fifo_dout_q2	std_logic_vector ( 23 downto 0 ) := ( others = > ' 0 ' )
dig_store_proc_ena	std_logic_vector ( 1 downto 0 ) := ( others = > ' 0 ' )
single_bus_state	SingleBusProcessing_machine := IDLE
digNshift_ena	std_logic := ' 0 '
digNshift_done	std_logic := ' 0 '
thr_chk_ena	std_logic := ' 0 '
ped_queue_ena	std_logic := ' 0 '
proc_ena	std_logic
tb5arr	std_logic_vector ( 4 downto 0 )
chan_mask	slv15 ( 4 downto 0 ) := ( others = > " 000000000000000 " )
digNshift_busy	std_logic := ' 0 '
main_samp_in_0	slv12 ( 14 downto 0 ) := ( others = > " 000000000000 " )
samples_valid	std_logic := ' 0 '
wave_fifo_wr_asic_q0	std_logic_vector ( 4 downto 0 ) := " 00001 "
thr_chk_busy	std_logic := ' 0 '
wave_fifo_wr_asic_q1	std_logic_vector ( 4 downto 0 ) := " 00001 "
new_mask_q0	slv15 ( 4 downto 0 ) := ( others = > " 000000000000000 " )
fifo_dout_q0	slv24 ( 14 downto 0 ) := ( others = > ( others = > ' 0 ' ) )
fifos_valid_q0	std_logic_vector ( 14 downto 0 ) := ( others = > ' 0 ' )
fifos_empty	std_logic_vector ( 14 downto 0 ) := ( others = > ' 0 ' )
fifo_rst	std_logic := ' 0 '
fifo_asic_sel	std_logic_vector ( 4 downto 0 ) := " 00001 "
fifo_chan_sel	std_logic_vector ( 3 downto 0 ) := ( others = > ' 0 ' )
fifo_rd_ena_q0	std_logic := ' 0 '
ped_queue_busy	std_logic := ' 0 '

Attributes
keep	string
keep	fifo_rst : signal is " true "
keep	all_fifos_empty : signal is " true "

Records
wave_fifo_din_t
wr_ena	std_logic_vector ( 14 downto 0 )
din	slv12 ( 14 downto 0 )

Instantiations
u0_i	TrigBit2Mask <Entity TrigBit2Mask>
digitizeandshiftoutdata_i	DigitizeAndShiftOutData <Entity DigitizeAndShiftOutData>
thresholdcheck_i	ThresholdCheck <Entity ThresholdCheck>
waveandpedstaging_ii	WaveAndPedStaging <Entity WaveAndPedStaging>
procwaveform_i	ProcWaveform <Entity ProcWaveform>
pedfetchqueue_i	PedFetchQueue <Entity PedFetchQueue>

Detailed Description

Definition at line 125 of file SingleBusProcessing.vhd.

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The documentation for this class was generated from the following file:

• klm_scint/source/SingleBusProcessing.vhd