ThresholdCheck Entity Reference

Inheritance diagram for ThresholdCheck:

Entities
Behavioral	architecture

Libraries
IEEE
work

Use Clauses
STD_LOGIC_1164
NUMERIC_STD
STD_LOGIC_MISC
STD_LOGIC_UNSIGNED
klm_scint_pkg	Package <klm_scint_pkg>

Generics
tb5_disambig_thr_g	std_logic_vector ( 11 downto 0 ) := " 000001000000 "
PED_AVG_g	std_logic_vector ( 11 downto 0 ) := " 110000000000 "

Ports
clk	in STD_LOGIC := ' 0 '
rst	in STD_LOGIC := ' 0 '
ena	in std_logic := ' 0 '
busy	out std_logic := ' 0 '
sample_data	in slv12 ( 14 downto 0 ) := ( others = > " 000000000000 " )
samples_valid	in std_logic := ' 0 '
digNshift_done	in std_logic := ' 0 '
chan_mask	in slv15 ( 4 downto 0 ) := ( others = > " 000000000000000 " )
asic	in std_logic_vector ( 4 downto 0 ) := ( others = > ' 0 ' )
wave_fifo_wr_ena	out std_logic_vector ( 14 downto 0 ) := ( others = > ' 0 ' )
wave_fifo_din	out slv12 ( 14 downto 0 ) := ( others = > " 000000000000 " )
wave_fifo_wr_asic	out std_logic_vector ( 4 downto 0 ) := " 00001 "
new_mask	out slv15 ( 4 downto 0 ) := ( others = > " 000000000000000 " )

Detailed Description

This module receives samples from 15 channels on one asic. It passes the samples which make it through the channel mask onto their designated FIFOs in WaveAndPedStaging.

If trigger-bit 5 is high (multihit), then a threshold check is performed on each channel; any channel which crosses threshold is flagged so that we only have to fetch pedestals for actual signals.

Definition at line 16 of file ThresholdCheck.vhd.

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The documentation for this class was generated from the following file:

• klm_scint/source/ThresholdCheck.vhd