Belle II KLM Scint Firmware  1
ThresholdCheck.vhd
1 library IEEE;
2 use IEEE.STD_LOGIC_1164.ALL;
3 use IEEE.NUMERIC_STD.ALL;
4 use IEEE.STD_LOGIC_MISC.ALL;
5 use IEEE.STD_LOGIC_UNSIGNED.ALL;
6 Library work;
7 use work.klm_scint_pkg.all;
8 
15 
16 entity ThresholdCheck is
17  Generic (
18  -- CoarsePedAdj : std_logic_vector(11 downto 0);
19  tb5_disambig_thr_g : std_logic_vector(11 downto 0) := "000001000000"; -- 64
20  PED_AVG_g : std_logic_vector(11 downto 0) := "110000000000" -- 3072
21  );
22  Port (
23  clk : in STD_LOGIC := '0';
24  rst : in STD_LOGIC := '0';
25  ena : in std_logic := '0';
26  busy : out std_logic := '0';
27 
28  -- control registers
29  -- N_readout_samples : in std_logic_vector(7 downto 0) := "01100000"; -- 96
30 
31  -- wires from ShiftOutSample
32  sample_data : in slv12(14 downto 0) := (others=>"000000000000");
33  samples_valid : in std_logic := '0';
34  -- sample_sel : in std_logic_vector(4 downto 0) := (others=>'0');
35  digNshift_done : in std_logic := '0';
36 
37  -- input parameters
38  chan_mask : in slv15(4 downto 0) := (others => "000000000000000"); -- enables storage fifos
39  asic : in std_logic_vector(4 downto 0) := (others=>'0');
40 
41  -- wires to WaveAndPedStaging
42  wave_fifo_wr_ena : out std_logic_vector(14 downto 0) := (others=>'0');
43  wave_fifo_din : out slv12(14 downto 0) := (others=>"000000000000");
44  wave_fifo_wr_asic : out std_logic_vector(4 downto 0) := "00001";
45 
46  -- threshold results for downstream processing
47  new_mask : out slv15(4 downto 0) := (others => "000000000000000")
48  );
49 end ThresholdCheck;
50 
51 architecture Behavioral of ThresholdCheck is
52 
53  -- constant BASELINE : slv12(31 downto 0) := ("100111000100", "100111000100", "100111000100", "100111000100",
54  -- "100111000100", "100111000100", "100111000100", "100111000100",
55  -- "100111000100", "100111000100", "100111000100", "100111000100",
56  -- "100111000100", "100111000100", "100111000100", "100111000100",
57  -- "100111000100", "100111000100", "100111000100", "100111000100",
58  -- "100111000100", "100111000100", "100111000100", "100111000100",
59  -- "100111000100", "100111000100", "100111000100", "100111000100",
60  -- "100111000100", "100111000100", "100111000100", "100111000100");
61  signal ena_i : std_logic_vector(1 downto 0) := (others => '0');
62  signal asic_i : integer range 0 to 4 := 0;
63 
64  type threshold_check_state_machine is
65  (
66  IDLE,
67  WAITING_FOR_SAMPLES,
68  FILLING_FIFOS
69  );
70  signal threshold_check_state : threshold_check_state_machine := IDLE;
71 
72 
73 begin
74 
75 
76  --detect start rising edge
77  process (clk, ena, ena_i)
78  begin
79  if rising_edge(clk) then
80  ena_i(1) <= ena_i(0);
81  ena_i(0) <= ena;
82  end if;
83  end process;
84 
85  process(clk, asic)
86  begin
87  if rising_edge(clk) then
88  for i in 0 to 4 loop
89  if asic(i) = '1' then
90  asic_i <= i;
91  exit;
92  end if;
93  end loop;
94  end if;
95  end process;
96 
97 
98  process(clk, rst, ena_i, samples_valid, sample_data,
99  chan_mask, digNshift_done)
100  begin
101  if rising_edge(clk) then
102  if rst = '1' then
103  new_mask <= (others => "000000000000000");
104  threshold_check_state <= IDLE;
105  else
106 
107  Case threshold_check_state is
108 
109  When IDLE =>
110  wave_fifo_wr_ena <= (others => '0');
111  if ( ena_i(1 downto 0) = "01" ) then
112  busy <= '1';
113  new_mask <= (others => "000000000000000");
114  threshold_check_state <= WAITING_FOR_SAMPLES;
115  else
116  -- wave_fifo_din <= (others => "000000000000");
117  busy <= '0';
118  threshold_check_state <= IDLE;
119  end if;
120 
121  -- Bounce back and forth between next two states while samples are coming in
122  when WAITING_FOR_SAMPLES =>
123  wave_fifo_wr_ena <= (others => '0');
124  if samples_valid = '1' then
125  for i in 0 to 14 loop
126  -- wave_fifo_din(i) <= "111111111111" - CoarsePedAdj - sample_data(i); -- inverter, baseline offset
127  wave_fifo_din(i) <= sample_data(i); -- passthrough
128  -- if sample_data(i) < (BASELINE(to_integer(unsigned(sample_sel))) - tb5_disambig_thr_g)
129  -- if sample_data(i) > (BASELINE(to_integer(unsigned(sample_sel))) + tb5_disambig_thr_g)
130  -- if sample_data(i) > (PED_AVG_g + tb5_disambig_thr_g)
131  if sample_data(i) < (PED_AVG_g - tb5_disambig_thr_g)
132  and chan_mask(asic_i)(i) = '1' then
133  new_mask(asic_i)(i) <= '1';
134  end if;
135  end loop;
136  threshold_check_state <= FILLING_FIFOS;
137  elsif digNshift_done = '1' then
138  -- wave_fifo_din <= (others => "000000000000");
139  busy <= '0';
140  threshold_check_state <= IDLE;
141  else
142  threshold_check_state <= WAITING_FOR_SAMPLES;
143  end if;
144 
145  when FILLING_FIFOS =>
146  wave_fifo_wr_ena <= chan_mask(asic_i);
147  wave_fifo_wr_asic <= (others => '0');
148  wave_fifo_wr_asic(asic_i) <= '1';
149  threshold_check_state <= WAITING_FOR_SAMPLES;
150 
151  When OTHERS =>
152  threshold_check_state <= IDLE;
153 
154  end case;
155  end if;
156  end if;
157  end process;
158 
159 end Behavioral;
klm_scint_pkg
Definition: klm_scint_pkg.vhd:7