design files for SCROD revB:

• schematic (pdf)
• instructions for making and soldering JTAG/timing cables (pdf) (svg)
• layout (pdf) top (jpeg) bottom (jpeg)
• gerbers
• assembly files (BoM, partial gerbers)
• annotated schematic for CAL fanout
• other:
  • power dissipation file for import into hyperlynx thermal (pwr)
  • trace lengths for LPDDR2 ram (xls)
  • list of changes
  • trace impedance calculation details
  • layer stackup (xls)
  • spreadsheet for TOP boardstack planning (estimated power draw, number of board-to-board interconnect pins required, number of FPGA IOs required, regulator power estimates, capacitor count, cable drop calculations, crossover wiring diagrams, ASIC-to-FPGA pin mapping, etc; xls)
  • boardstack block diagram (svg) (png)
  • Zynq '045 ball assignment and PS MIO pin configuration (ods)
  • MIO at-a-glance modified for SCROD revB (svg) (png)
  • individual regulator simulation results (png)
  • regulator sequencing simulation files (PS and PL; LTSpiceIV) (results png)
  • calibration circuit simulation (LTspice) result (png)
  • calibration circuit simulation for whole boardstack (LTspice) result (png)
  • FPGA IO location constraints file (ucf)
• datasheets for components on SCROD revB:
  • n-channel FET (AO7400)
  • p-channel FET (AO7401)
  • p-channel power mosfet (IRLR7821)
  • Linear Regulator (LT3055)
  • Linear Regulator (LT3086)
  • MUX 2to1 (sn74aup1t157)
  • DEMUX 1to2 (sn74lvc1g18)
  • Quad High Speed Differential Receiver (sn65lvdt348pw)
  • High Speed Differential Line Driver (sn65lvds1)
  • USB Transceiver (USB3320)
  • ADC (AD7923)
  • QSPI Flash (S25FL128SAGBHIA)
  • i2c eeprom (24LC64T-I/MC)
  • i2c humidity sensor (HTU21D)
  • i2c temperature sensor (STTS751-1WB3F)
  • buffer amplifier (lmh6559)
  • and gate (SN74AUP1G08DCKR)
  • d flip-flop (SN74LVC1G175DCKR)
  • green LED (SML-P11MTT86)
  • SoC/FPGA datasheet (zynq '045)
  • SoC/FPGA technical reference manual (zynq '045)
  • SoC/FPGA other (zynq)
  • board-to-board interconnect (FX8C-100S-SV5)
  • SFP fiber transceiver (AFBR-57D7APZ)
  • SFP+ cage (747540101)
  • CDCLVD1208RHDT (LVDS fanout with low additive jitter)

design files for SCROD "fake" revB (mechanical mockup v1):

• schematic (pdf)
• layout (pdf) (png)
• gerbers

design files for SCROD revA3:

• schematic (pdf)
• layout (pdf)
• gerbers
• assembly files (XYRS, BoM, partial gerbers)
• trace impedance calculation details

design files for SCROD revA2:

• schematic (pdf)
• layout
• gerbers

design files for SCROD revA:

• schematic (pdf)
• layout (pdf)
• gerbers

also see:

• SCROD revA2 (info on revA2 revision of SCROD)