Behavioral Architecture Reference

Processes
b2tt_rst_ppln	( clk , rst )
	SPS_RAM:
SC_buffering	( clk , fifo_rst_r )
ped_sub	( clk , ped_sub_ena , fifo_dout , fifo_drdy )
proc_fsm_ena_sel	( clk , ena , feat_ext_ena , avg_peds_ena_i , measure_peds , avg_peds_ena , avg_peds_rd_ena , avg_peds_chn_sel , avg_peds_asic_mask , feat_ext_chn_sel , feat_ext_rd_ena_q1 , feat_ext_asic_mask )
read_wave	( clk , stream_N_ro_samps_ena , N_readout_samples )
hit_chs_lgc	( clk , ch_mask_q1 )
Extract_Features	( clk , b2tt_rst (b2tt_rst 'left) , fifos_empty , feat_ext_ena , ch_mask , win_samp_start , LE_time_thresh , wave_data , wave_drdy , win_samp_start_i , cur_asic , peak_i , le_charge , N_readout_samples , any_ch_hit , asics_hit , ch_mask_q2 )
wr_debug_wave	( clk , write_debug_wave_header , write_debug_wave_footer , daq_chan_i , win_samp_start_i , cur_asic , wave_data , peak_i , le_time_i , wave_drdy )
tx_features	( clk , tx_features_ena , peak_i , le_time_i , daq_chan_i , last_hit_i , daq_chan_i , last_hit_i , rx_features_ack )
fill_SPS	( clk , SPS_hist_rd_addr , fill_SPS_hist_ena , le_charge , sps_reset , i_SPS_hist_rd_data )
avg_and_wr_peds	( clk , avg_peds_ena_i , sram_asic_addr_i , wave_div_NBA , wave_drdy , avg_peds_rd_ena , avg_peds_chn_sel , sram_samp_addr_i )

Types
feat_ext_state_machine	( CHECK_FIFOS_RDY , IDLE , WAIT_VALID , CHECK_VALID , LOOPING_JOBS , WAITING_FIFO_READ_LAG , LOOPING_SAMPLES , CHECK_DONE )
	Extract_Features:
debug_fifo_fill_state_machine	( IDLE , WRITE_CHAN_AND_SAMP , WRITE_ASIC_AND_WINDOW , WRITING , WRITE_LAST_WORD , WRITE_EOF , STOP )
	wr_debug_wave:
tx_features_state_machine	( IDLE , WAIT_TX )
	tx_features:
fill_SPS_hist_state_machine	( IDLE , READ_RAM , WRITE_TO_RAM , RESETTING )
	fill_SPS:
average_peds_state_machine	( IDLE , ASIC_LOOP , CHANNEL_LOOP , READ_ONE_MORE , AVERAGE_EVEN_SAMPLE , AVERAGE_ODD_SAMPLE , WAIT_PED_WRITER )
	avg_and_wr_peds:

Signals
b2tt_rst	std_logic_vector ( B2TT_RST_PPLN_STGS- 1 downto 0 )
	b2tt_rst_ppln
fifo_rst_r	std_logic_vector ( FIFO_RST_PPLN_STGS- 1 downto 0 ) := ( others = > ' 0 ' )
	SC_buffering:
wave_data	std_logic_vector ( 11 downto 0 ) := ( others = > ' 0 ' )
	ped_sub:
wave_drdy	std_logic := ' 0 '
wave_div_NBA	std_logic_vector ( 11 downto 0 ) := ( others = > ' 0 ' )
ped_data	std_logic_vector ( 11 downto 0 ) := ( others = > ' 0 ' )
feat_ext_ena	std_logic_vector ( 1 downto 0 ) := ( others = > ' 0 ' )
	proc_fsm_ena_sel:
avg_peds_ena_i	std_logic_vector ( 1 downto 0 ) := ( others = > ' 0 ' )
feat_ext_rd_ena_q1	std_logic := ' 0 '
	read_wave:
any_ch_hit	std_logic := ' 0 '
	hit_chs_lgc:
asics_hit	std_logic_vector ( 4 downto 0 ) := ( others = > ' 0 ' )
ch_mask_q2	slv15 ( 4 downto 0 ) := ( others = > " 000000000000000 " )
feat_ext_state	feat_ext_state_machine := IDLE
write_debug_wave_header	std_logic := ' 0 '
write_debug_wave_footer	std_logic := ' 0 '
fill_SPS_hist_ena	std_logic := ' 0 '
ch_mask_q1	slv15 ( 4 downto 0 ) := ( others = > " 000000000000000 " )
tx_features_ena	std_logic := ' 0 '
stream_N_ro_samps_ena	std_logic := ' 0 '
peak_i	std_logic_vector ( 11 downto 0 ) := ( others = > ' 0 ' )
le_charge	std_logic_vector ( 13 downto 0 ) := ( others = > ' 0 ' )
le_time_i	std_logic_vector ( 13 downto 0 ) := ( others = > ' 0 ' )
last_hit_i	std_logic := ' 0 '
cur_asic	integer range 0 to 4 := 0
feat_ext_busy	std_logic := ' 0 '
feat_ext_asic_mask	std_logic_vector ( 4 downto 0 ) := " 00001 "
feat_ext_chn_sel	std_logic_vector ( 3 downto 0 ) := ( others = > ' 0 ' )
daq_chan_i	std_logic_vector ( 6 downto 0 ) := ( others = > ' 0 ' )
win_samp_start_i	slv14 ( 4 downto 0 ) := ( others = > ( others = > ' 0 ' ) )
debug_fifo_fill_state	debug_fifo_fill_state_machine := IDLE
tx_features_state	tx_features_state_machine := IDLE
tx_features_busy	std_logic := ' 0 '
fill_SPS_hist_state	fill_SPS_hist_state_machine := IDLE
SPS_hist_address	std_logic_vector ( 9 downto 0 ) := ( others = > ' 0 ' )
SPS_hist_wr_ena	std_logic_vector ( 0 downto 0 ) := " 0 "
SPS_hist_wr_data	std_logic_vector ( 15 downto 0 ) := ( others = > ' 0 ' )
i_SPS_hist_rd_data	slv16 ( STAT_REG_PPLN_STGS- 1 downto 0 ) := ( others = > ( others = > ' 0 ' ) )
avg_peds_state	average_peds_state_machine := IDLE
avg_peds_rd_ena	std_logic := ' 0 '
avg_peds_chn_sel	std_logic_vector ( 3 downto 0 ) := ( others = > ' 0 ' )
avg_peds_asic_mask	std_logic_vector ( 4 downto 0 ) := " 00001 "
sram_asic_addr_i	std_logic_vector ( 2 downto 0 ) := ( others = > ' 0 ' )
sram_samp_addr_i	std_logic_vector ( 3 downto 0 ) := ( others = > ' 0 ' )

Instantiations
sps_ram	spsblockram

Detailed Description

Definition at line 103 of file ProcWaveform.vhd.

Member Function Documentation

avg_and_wr_peds()

avg_and_wr_peds (   clk ,   avg_peds_ena_i ,   sram_asic_addr_i ,   wave_div_NBA ,   wave_drdy ,   avg_peds_rd_ena ,   avg_peds_chn_sel ,   sram_samp_addr_i   )

Process

FSM checks with PedestalWriter.vhd's bus A/B arbiter, then reads and averages two pedestals at a time (called even/odd here). These two 12-bit pedestal values are then writen across 3 8-bit SRAM address.

Definition at line 669 of file ProcWaveform.vhd.

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The documentation for this class was generated from the following file:

• klm_scint/source/ProcWaveform.vhd