Belle II KLM Scint Firmware  1
ProcWaveform.vhd
1 library IEEE;
2 use IEEE.STD_LOGIC_1164.ALL;
3 use IEEE.NUMERIC_STD.ALL;
4 use IEEE.STD_LOGIC_MISC.ALL;
5 use IEEE.STD_LOGIC_UNSIGNED.ALL;
6 Library work;
7 use work.klm_scint_pkg.all;
8 
29 
30 
31 
32 entity ProcWaveform is
33  generic (
34  baseline_g : std_logic_vector(11 downto 0);
35  WAVE_MEM_DEPTH : integer := 4;
36  B2TT_RST_PPLN_STGS : integer := 5;
37  STAT_REG_PPLN_STGS : integer := 5;
38  FIFO_RST_PPLN_STGS : integer := 6;
39  SPSBlockRAM_READ_LATENCY : integer := 6; -- from pipelined output selected in ISE core generator
40  N_BITS_AVG_g : integer
41  );
42  port (
43  clk : in std_logic := '0';
44  rst : in std_logic := '0';
45  ena : in std_logic := '0';
46 
48  ped_sub_ena : in std_logic;
49  measure_peds : in std_logic;
50  stream_peds : in std_logic;
51  N_readout_samples : in std_logic_vector(7 downto 0);
52  LE_time_thresh : in std_logic_vector(11 downto 0) := "000000110010"; -- 50
53 
55  busy : out std_logic := '0';
56  debug_we : out std_logic := '0';
57  debug_wave : out std_logic_vector(11 downto 0) := (others=>'0');
58 
60  win_samp_start : in slv14(4 downto 0) := (others=>(others=>'0'));
61  ch_mask : in slv15(4 downto 0) := (others=>"000000000000000");
62 
64  fifo_rst : out std_logic := '0';
65  fifo_asic_sel : out std_logic_vector(4 downto 0) := (others=>'0');
66  fifo_chan_sel : out std_logic_vector(3 downto 0) := (others=>'0');
67  fifo_rd_ena : out std_logic := '0';
68  fifo_dout : in std_logic_vector(23 downto 0) := (others=>'0');
69  fifo_drdy : in std_logic := '0';
70  fifos_empty : in std_logic := '0';
71 
73  rx_features_ack : in std_logic := '0';
74  rx_features_ena : out std_logic := '0';
75  last_hit : out std_logic := '0';
76  peak : out std_logic_vector(11 downto 0) := (others => '0');
77  le_time : out std_logic_vector(13 downto 0) := (others => '0');
78  daq_chan : out std_logic_vector(6 downto 0) := (others => '0');
79 
81  avg_peds_ena : in std_logic := '0';
82  avg_peds_busy : out std_logic := '0';
83  wr_peds2sram_ena : out std_logic := '0';
84  wr_peds2sram_ack : in std_logic := '0';
85  even_ped : out std_logic_vector(11 downto 0) := (others => '0');
86  odd_ped : out std_logic_vector(11 downto 0) := (others => '0');
87  sram_asic_addr : out std_logic_vector(2 downto 0) := (others => '0');
88  sram_chan_addr : out std_logic_vector(3 downto 0) := (others => '0');
89  sram_samp_addr : out std_logic_vector(3 downto 0) := (others => '0');
90  fe_dbg : out std_logic_vector(1 downto 0) := "00";
91 
93  sps_reset : in std_logic := '0';
94  SPS_hist_rd_addr : in std_logic_vector(9 downto 0) := (others => '0');
95  SPS_hist_rd_data : out std_logic_vector(15 downto 0) := (others => '0')
96 
97 
98  );
99 end ProcWaveform;
100 
101 
102 
103 architecture Behavioral of ProcWaveform is
104 
105 -- SYNCHRONOUS SIGNALS BY PROCESS WHICH DRIVES THEM
106 
108  signal b2tt_rst : std_logic_vector(B2TT_RST_PPLN_STGS-1 downto 0);
109 
111  signal fifo_rst_r : std_logic_vector(FIFO_RST_PPLN_STGS-1 downto 0) := (others=>'0');
112 
114  signal wave_data : std_logic_vector(11 downto 0) := (others=>'0');
115  signal wave_drdy : std_logic := '0';
116  signal wave_div_NBA : std_logic_vector(11 downto 0) := (others=>'0');
117  signal ped_data : std_logic_vector(11 downto 0) := (others=>'0');
118 
120  signal feat_ext_ena : std_logic_vector(1 downto 0) := (others => '0');
121  signal avg_peds_ena_i : std_logic_vector(1 downto 0) := (others => '0');
122 
124  signal feat_ext_rd_ena_q1 : std_logic := '0';
125 
127  signal any_ch_hit : std_logic := '0';
128  signal asics_hit : std_logic_vector(4 downto 0) := (others=>'0');
129  signal ch_mask_q2 : slv15(4 downto 0) := (others=>"000000000000000");
130 
132  type feat_ext_state_machine is (CHECK_FIFOS_RDY, IDLE, WAIT_VALID, CHECK_VALID,
133  LOOPING_JOBS, WAITING_FIFO_READ_LAG, LOOPING_SAMPLES, CHECK_DONE);
134  signal feat_ext_state : feat_ext_state_machine := IDLE;
135  signal write_debug_wave_header : std_logic := '0';
136  signal write_debug_wave_footer : std_logic := '0';
137  signal fill_SPS_hist_ena : std_logic := '0';
138  signal ch_mask_q1 : slv15(4 downto 0) := (others=>"000000000000000");
139  signal tx_features_ena : std_logic := '0';
140  signal stream_N_ro_samps_ena : std_logic := '0';
141  signal peak_i : std_logic_vector(11 downto 0) := (others => '0');
142  signal le_charge : std_logic_vector(13 downto 0) := (others => '0');
143  --signal charge_p : std_logic_vector(19 downto 0) := (others => '0');
144  --signal charge_n : std_logic_vector(19 downto 0) := (others => '0');
145  signal le_time_i : std_logic_vector(13 downto 0) := (others => '0');
146  signal last_hit_i : std_logic := '0';
147  signal cur_asic : integer range 0 to 4 := 0;
148  signal feat_ext_busy : std_logic := '0';
149  signal feat_ext_asic_mask : std_logic_vector(4 downto 0) := "00001";
150  signal feat_ext_chn_sel : std_logic_vector(3 downto 0) := (others=>'0');
151  signal daq_chan_i : std_logic_vector(6 downto 0) := (others => '0');
152  signal win_samp_start_i : slv14(4 downto 0) := (others=>(others=>'0'));
153 
155  type debug_fifo_fill_state_machine is (IDLE, WRITE_CHAN_AND_SAMP,
156  WRITE_ASIC_AND_WINDOW, WRITING, WRITE_LAST_WORD, WRITE_EOF, STOP );
157  signal debug_fifo_fill_state : debug_fifo_fill_state_machine := IDLE;
158 
160  type tx_features_state_machine is (IDLE, WAIT_TX);
161  signal tx_features_state : tx_features_state_machine := IDLE;
162  signal tx_features_busy : std_logic := '0';
163 
165  type fill_SPS_hist_state_machine is (IDLE, READ_RAM, WRITE_TO_RAM, RESETTING);
166  signal fill_SPS_hist_state : fill_SPS_hist_state_machine := IDLE;
167  --signal SPS_hist_address : std_logic_vector(13 downto 0) := (others=>'0');
168  signal SPS_hist_address : std_logic_vector(9 downto 0) := (others=>'0');
169  signal SPS_hist_wr_ena : std_logic_vector(0 downto 0) := "0"; -- required type (due to ISE core gen)
170  signal SPS_hist_wr_data : std_logic_vector(15 downto 0) := (others=>'0');
171  signal i_SPS_hist_rd_data : slv16(STAT_REG_PPLN_STGS - 1 downto 0) := (others=>(others=>'0'));
172 
174  type average_peds_state_machine is (IDLE, ASIC_LOOP, CHANNEL_LOOP, READ_ONE_MORE,
175  AVERAGE_EVEN_SAMPLE, AVERAGE_ODD_SAMPLE, WAIT_PED_WRITER);
176  signal avg_peds_state : average_peds_state_machine := IDLE;
177  signal avg_peds_rd_ena : std_logic := '0';
178  signal avg_peds_chn_sel : std_logic_vector(3 downto 0) := (others => '0');
179  signal avg_peds_asic_mask : std_logic_vector(4 downto 0) := "00001";
180  signal sram_asic_addr_i : std_logic_vector(2 downto 0) := (others => '0');
181  signal sram_samp_addr_i : std_logic_vector(3 downto 0) := (others => '0');
182 
183 -- ASYNCHRONOUSLY DRIVEN SIGNALS
184  --signal charge_s : std_logic_vector(19 downto 0) := (others => '0');
185 -- SIGNALS DRIVEN BY INSTANTIATED ENTITIES
187 
188 
189 
190 
191 begin
192 --------------------- ASYNCHRONOUS LOGIC ---------------------------------------------
193  fifo_rst <= fifo_rst_r(fifo_rst_r'left);
194  busy <= feat_ext_busy or tx_features_busy;
195  sram_asic_addr <= sram_asic_addr_i;
196  sram_chan_addr <= avg_peds_chn_sel;
197  sram_samp_addr <= sram_samp_addr_i;
198  -- charge_s <= charge_n - charge_p;
199 
200 
201 
202 
203 --------------------- SYNCHRONOUS LOGIC ---------------------------------------------
204  b2tt_rst_ppln: process(clk, rst)
205  begin
206  if rising_edge(clk) then
207  b2tt_rst <= b2tt_rst(b2tt_rst'left - 1 downto 0) & rst;
208  end if;
209  end process;
210 
211 
212 
213  SC_buffering: process(clk, fifo_rst_r)
214  begin
215  if rising_edge(clk) then
216  fifo_rst_r(fifo_rst_r'left downto 1) <= fifo_rst_r(fifo_rst_r'left - 1 downto 0);
217  end if;
218  end process;
219 
220 
221 
222  ped_sub: process(clk, ped_sub_ena, fifo_dout, fifo_drdy)
223  begin
224  if rising_edge(clk) then
225  wave_drdy <= fifo_drdy;
226  wave_div_NBA <= fifo_dout(N_BITS_AVG_g + 11 downto N_BITS_AVG_g); -- divide by 2**NBA
227  ped_data <= fifo_dout(23 downto 12); -- for debug
228  if ped_sub_ena = '1' then
229  wave_data <= baseline_g + fifo_dout(11 downto 0) - fifo_dout(23 downto 12);
230  else
231  wave_data <= fifo_dout(11 downto 0);
232  end if;
233  end if;
234  end process ped_sub;
235 
236 
237 
238  proc_fsm_ena_sel: process (clk, ena, feat_ext_ena, avg_peds_ena_i, measure_peds,
239  avg_peds_ena, avg_peds_rd_ena, avg_peds_chn_sel,
240  avg_peds_asic_mask, feat_ext_chn_sel,
241  feat_ext_rd_ena_q1, feat_ext_asic_mask)
242  begin
243  if rising_edge(clk) then
244  feat_ext_ena(1) <= feat_ext_ena(0);
245  avg_peds_ena_i(1) <= avg_peds_ena_i(0);
246  if measure_peds = '1' then
247  avg_peds_ena_i(0) <= avg_peds_ena;
248  fifo_rd_ena <= avg_peds_rd_ena;
249  fifo_chan_sel <= avg_peds_chn_sel;
250  fifo_asic_sel <= avg_peds_asic_mask;
251  else
252  feat_ext_ena(0) <= ena;
253  fifo_rd_ena <= feat_ext_rd_ena_q1;
254  fifo_chan_sel <= feat_ext_chn_sel;
255  fifo_asic_sel <= feat_ext_asic_mask;
256  end if;
257  end if;
258  end process proc_fsm_ena_sel;
259 
260 
261 
262  read_wave: process(clk, stream_N_ro_samps_ena, N_readout_samples)
263  variable count : integer range 0 to 255 := 0;
264  begin
265  if rising_edge(clk) then
266  if (stream_N_ro_samps_ena = '1' or count > 0) and count <= N_readout_samples then
267  count := count + 1;
268  feat_ext_rd_ena_q1 <= '1';
269  else
270  count := 0;
271  feat_ext_rd_ena_q1 <= '0';
272  end if;
273  end if;
274  end process read_wave;
275 
276 
277 
278  hit_chs_lgc: process(clk, ch_mask_q1)
279  begin
280  if rising_edge(clk) then
281  any_ch_hit <= or_reduce(ch_mask_q1(0)) or
282  or_reduce(ch_mask_q1(1)) or
283  or_reduce(ch_mask_q1(2)) or
284  or_reduce(ch_mask_q1(3)) or
285  or_reduce(ch_mask_q1(4));
286  for i in 0 to 4 loop
287  asics_hit(i) <= or_reduce(ch_mask_q1(i));
288  end loop;
289  ch_mask_q2 <= ch_mask_q1;
290  end if;
291  end process;
292 
293 
294 
295  Extract_Features: process(clk, b2tt_rst(b2tt_rst'left), fifos_empty, feat_ext_ena,
296  ch_mask, win_samp_start, LE_time_thresh,
297  wave_data, wave_drdy, win_samp_start_i, cur_asic,
298  peak_i, le_charge, N_readout_samples, --use_ftsw_trig, -- use_loop_trig,
299  any_ch_hit, asics_hit, ch_mask_q2)
300  variable int_count : integer range 0 to 4 := 0;
301  -- variable ch_mask_q1 : slv15(4 downto 0) := (others=>"000000000000000");
302  variable count : std_logic_vector(7 downto 0) := (others => '0');
303  variable le_time_found : std_logic := '0';
304  variable wave_mem : slv12(WAVE_MEM_DEPTH - 1 downto 0) := (others => "000000000000");
305  begin
306  if rising_edge(clk) then
307  if b2tt_rst(b2tt_rst'left) = '1' then
308  -- feat_ext_chn_sel <= "1111";
309  ch_mask_q1 <= (others=>(others=>'0'));
310  feat_ext_state <= CHECK_FIFOS_RDY;
311  else
312  Case feat_ext_state is
313 
314  When CHECK_FIFOS_RDY =>
315  fe_dbg <= "11";
316  if fifos_empty = '1' then
317  fifo_rst_r(0) <= '0';
318  feat_ext_state <= IDLE;
319  else
320  fifo_rst_r(0) <= '1';
321  feat_ext_state <= CHECK_FIFOS_RDY;
322  end if;
323 
324  When IDLE =>
325  fe_dbg <= "00";
326  int_count := 0;
327  feat_ext_chn_sel <= "0000";
328  -- feat_ext_asic_mask <= "00001";
329  stream_N_ro_samps_ena <= '0';
330  fill_SPS_hist_ena <= '0';
331  -- write_debug_wave_ena <= '0';
332  tx_features_ena <= '0';
333  -- null_hit_i <= '1';
334  peak_i <= (others=>'0');
335  le_charge <= (others=>'0');
336  -- charge_p <= (others=>'0');
337  -- charge_n <= (others=>'0');
338  le_time_i <= (others=>'0');
339  last_hit_i <= '0';
340  if feat_ext_ena(1 downto 0) = "01" then
341  last_hit_i <= '0';
342  ch_mask_q1 <= ch_mask;
343  win_samp_start_i <= win_samp_start;
344  feat_ext_busy <= '1';
345  feat_ext_state <= WAIT_VALID;
346  else
347  feat_ext_busy <= '0';
348  feat_ext_state <= IDLE;
349  end if;
350 
351  When WAIT_VALID =>
352  if int_count < 2 then -- MAGIC NUMBER -- FIXME
353  int_count := int_count + 1;
354  feat_ext_state <= WAIT_VALID;
355  else
356  int_count := 0;
357  feat_ext_state <= CHECK_VALID;
358  end if;
359 
360  When CHECK_VALID =>
361  if any_ch_hit = '0' then -- all hits on bus (single or multi) failed threshold check, send null packet
362  last_hit_i <= '1';
363  -- null_hit_i <= '1';
364  tx_features_ena <= '1';
365  feat_ext_state <= CHECK_DONE;
366  else
367  last_hit_i <= '0';
368  -- null_hit_i <= '0';
369  feat_ext_state <= LOOPING_JOBS;
370  end if;
371 
372  When LOOPING_JOBS =>
373  fe_dbg <= "01";
374  write_debug_wave_footer <= '0';
375  fill_SPS_hist_ena <= '0';
376  last_hit_i <= '0';
377  count := (others => '0');
378  le_time_found := '0';
379  tx_features_ena <= '0';
380  if int_count = 4 then-- increment asic counter
381  int_count := 0;
382  else
383  int_count := int_count + 1;
384  end if;
385  feat_ext_asic_mask <= (others => '0'); -- 5 bit asic mask
386  feat_ext_asic_mask(int_count) <= '1';
387  cur_asic <= int_count;
388  priority_encoder: for i in 0 to 14 loop
389  if (ch_mask_q2(int_count)(i)) = '1' then
390  feat_ext_chn_sel <= std_logic_vector(to_unsigned(i, 4));
391  daq_chan_i <= std_logic_vector(to_unsigned( int_count*15 + i , 7));
392  ch_mask_q1(int_count)(i) <= '0';
393  exit priority_encoder;
394  end if;
395  end loop;
396  if asics_hit(int_count) = '1' then
397  stream_N_ro_samps_ena <= '1';
398  feat_ext_state <= WAITING_FIFO_READ_LAG;
399  else
400  stream_N_ro_samps_ena <= '0';
401  feat_ext_state <= LOOPING_JOBS;
402  end if;
403 
404 
405  When WAITING_FIFO_READ_LAG => -- about 8 clocks
406  write_debug_wave_header <= '1'; -- x"50F", win, chan -- 8 clocks here covers case when still writing EOF
407  stream_N_ro_samps_ena <= '0';
408  if wave_drdy = '0' then
409  feat_ext_state <= WAITING_FIFO_READ_LAG;
410  else
411  le_time_i <= (win_samp_start_i(cur_asic)); --(others => '0');
412  peak_i <= (others => '0');
413  le_charge <= (others => '0');
414  -- charge_p <= (others => '0');
415  -- charge_n <= (others => '0');
416  wave_mem(0) := wave_data;
417  count := "00000001";
418  feat_ext_state <= LOOPING_SAMPLES;
419  end if;
420 
421 
422  When LOOPING_SAMPLES =>
423  write_debug_wave_header <= '0';
424  fe_dbg <= "10";
425  -- time (ns) count-2 count-1 count
426  -- <-----------------------------------------------|--->
427  -- . . . wave_mem(1) wave_mem(0) wave_data
428  if ((count > 0) and (le_time_found = '0') and (wave_data < LE_time_thresh) and (wave_mem(0) > LE_time_thresh)) then
429  if (LE_time_thresh - wave_data) > (wave_mem(0) - LE_time_thresh) then
430  le_time_i <= (win_samp_start_i(cur_asic) + count);
431  else
432  le_time_i <= (win_samp_start_i(cur_asic) + count + '1');
433  end if;
434  le_time_found := '1';
435  end if;
436  -- check for extremum
437  if ((count > "00000001")
438  and (wave_mem(0) < wave_mem(1))
439  and (wave_mem(0) <= wave_data)
440  and (wave_mem(0) < baseline_g - peak_i))
441  then
442  peak_i <= baseline_g - wave_mem(0);
443  -- measure leading-edge charge
444  if (count > "00000100") then
445  le_charge <= (baseline_g & "00")
446  - ("00" & wave_mem(0))
447  - ("00" & wave_mem(1))
448  - ("00" & wave_mem(2))
449  - ("00" & wave_mem(3));
450  end if;
451  end if;
452  -- sum up charge
453  -- if wave_data <= baseline_g then
454  -- charge_n <= charge_n + baseline_g - wave_data;
455  -- else
456  -- charge_p <= charge_p + wave_data - baseline_g;
457  -- end if;
458  -- check & increment counter, shift sample into memory
459  if count < N_readout_samples - '1' then
460  count := count + '1';
461  for i in WAVE_MEM_DEPTH - 1 downto 1 loop
462  wave_mem(i) := wave_mem(i-1);
463  end loop;
464  wave_mem(0) := wave_data;
465  feat_ext_state <= LOOPING_SAMPLES;
466  else
467  if any_ch_hit = '0' then
468  last_hit_i <= '1';
469  feat_ext_state <= CHECK_DONE;
470  else
471  feat_ext_state <= LOOPING_JOBS;
472  end if;
473  write_debug_wave_footer <= '1'; -- q, t, x"EOF"
474  tx_features_ena <= '1';
475  -- fill_SPS_hist_ena <= use_loop_trig and not use_ftsw_trig;
476  fill_SPS_hist_ena <= '1';
477  end if;
478 
479  When CHECK_DONE =>
480  write_debug_wave_footer <= '0';
481  fill_SPS_hist_ena <= '0';
482  tx_features_ena <= '0';
483  if fifos_empty = '0' then
484  feat_ext_state <= CHECK_FIFOS_RDY;
485  else
486  feat_ext_state <= IDLE;
487  end if;
488 
489  -- When OTHERS =>
490  -- feat_ext_state <= IDLE;
491 
492  end case;
493  end if;
494  end if;
495  end process Extract_Features;
496 
497 
498 
499  --fill_debug_fifos_with_waveform_data
500  -- FSM enable issued in Extract_Features process block
501  wr_debug_wave: process(clk, write_debug_wave_header, write_debug_wave_footer,
502  daq_chan_i, win_samp_start_i, cur_asic,
503  wave_data, peak_i, le_time_i, wave_drdy)
504  begin
505  if rising_edge(clk) then
506  case debug_fifo_fill_state is
507  When IDLE =>
508  if write_debug_wave_header = '1' then
509  debug_we <= '1';
510  debug_wave <= x"50F"; -- i.e. "SOF"
511  debug_fifo_fill_state <= WRITE_CHAN_AND_SAMP;
512  else
513  debug_we <= '0';
514  debug_wave <= x"000";
515  debug_fifo_fill_state <= IDLE;
516  end if;
517  When WRITE_CHAN_AND_SAMP =>
518  debug_wave <= daq_chan_i & win_samp_start_i(cur_asic)(4 downto 0);
519  debug_fifo_fill_state <= WRITE_ASIC_AND_WINDOW;
520  When WRITE_ASIC_AND_WINDOW =>
521  debug_wave <= std_logic_vector(to_unsigned(cur_asic, 3)) & win_samp_start_i(cur_asic)(13 downto 5);
522  debug_fifo_fill_state <= WRITING;
523  When WRITING =>
524  if write_debug_wave_footer = '0' then
525  debug_we <= wave_drdy; -- aligned with wave/ped_data
526  if stream_peds = '1' then
527  debug_wave <= ped_data;
528  else
529  debug_wave <= wave_data;
530  end if;
531  debug_fifo_fill_state <= WRITING;
532  else
533  debug_we <= '1';
534  debug_wave <= peak_i;
535  debug_fifo_fill_state <= WRITE_LAST_WORD;
536  end if;
537  When WRITE_LAST_WORD =>
538  debug_wave <= le_time_i(11 downto 0);
539  debug_fifo_fill_state <= WRITE_EOF;
540  When WRITE_EOF =>
541  debug_wave <= x"E0F";
542  debug_fifo_fill_state <= IDLE;
543  -- When STOP =>
544  -- debug_wave <= x"000";
545  -- debug_we <= '0';
546  -- debug_fifo_fill_state <= IDLE;
547  When OTHERS =>
548  debug_fifo_fill_state <= IDLE;
549  end case;
550  end if;
551  end process wr_debug_wave;
552 
553 
554 
555  -- Transmit Features To Hit Builder
556  -- This FSM is enabled by the "Extract_Features" process block above
557  tx_features: process(clk, tx_features_ena, peak_i, le_time_i,
558  daq_chan_i, last_hit_i, daq_chan_i, last_hit_i,
559  rx_features_ack)
560  begin
561  if rising_edge(clk) then
562  Case tx_features_state is
563 
564  When IDLE =>
565  if tx_features_ena = '1' then
566  rx_features_ena <= '1';
567  tx_features_busy <= '1';
568  -- null_hit <= null_hit_i;
569  peak <= peak_i;
570  le_time <= le_time_i;
571  daq_chan <= daq_chan_i;
572  last_hit <= last_hit_i;
573  tx_features_state <= WAIT_TX;
574  else
575  rx_features_ena <= '0';
576  tx_features_busy <= '0';
577  tx_features_state <= IDLE;
578  end if;
579 
580  When WAIT_TX =>
581  if rx_features_ack = '0' then
582  tx_features_state <= WAIT_TX;
583  else
584  rx_features_ena <= '0';
585  tx_features_state <= IDLE;
586  end if;
587 
588  -- When OTHERS =>
589  -- tx_features_state <= IDLE;
590 
591  end case;
592  end if;
593  end process tx_features;
594 
595 
596 
597  -- create_single_photon_spectra
598  -- FSM enable issued in Extract_Features process block
599  -- FSM stays in IDLE state when transmitting data to status registers for readback
600  fill_SPS: process(clk, SPS_hist_rd_addr, fill_SPS_hist_ena, --peak_i, charge_s, charge_n, charge_s,
601  le_charge, sps_reset, i_SPS_hist_rd_data)
602  variable count : std_logic_vector(9 downto 0);
603  begin
604  if rising_edge(clk) then
605 
606  -- pipelined output to reg interface
607  i_SPS_hist_rd_data(i_SPS_hist_rd_data'left downto 1) <= i_SPS_hist_rd_data(i_SPS_hist_rd_data'left - 1 downto 0);
608  SPS_hist_rd_data <= i_SPS_hist_rd_data(i_SPS_hist_rd_data'left);
609 
610  if sps_reset = '1' then
611  count := (others=> '0');
612  fill_SPS_hist_state <= RESETTING;
613  else
614 
615  case( fill_SPS_hist_state ) is
616 
617  when IDLE =>
618  count := (others=>'0');
619  SPS_hist_wr_ena <= "0";
620  SPS_hist_address <= SPS_hist_rd_addr; -- wired to regiter interface
621  -- if fill_SPS_hist_ena = '1' and peak_i <= "11011010" then -- 2^14 addressess allows 218 bins per daq_chan
622  -- if fill_SPS_hist_ena = '1' and charge_n > charge_p and charge_s <= "0000100000000000000" then -- resolution of 1 adc count for smallish waveforms, single chan
623  if fill_SPS_hist_ena = '1' and le_charge(13 downto 10) = "0000" then -- 1024 bins
624  -- SPS_hist_address <= std_logic_vector(to_unsigned(to_integer(unsigned(daq_chan_i))*218 + to_integer(unsigned(peak_i)), 14));
625  -- SPS_hist_address <= charge_s(13 downto 0);
626  SPS_hist_address <= le_charge(9 downto 0);
627  fill_SPS_hist_state <= READ_RAM;
628  else
629  fill_SPS_hist_state <= IDLE;
630  end if;
631 
632  when READ_RAM =>
633  if count < SPSBlockRAM_READ_LATENCY then
634  count := count + 1;
635  fill_SPS_hist_state <= READ_RAM;
636  else
637  count := (others=>'0');
638  SPS_hist_wr_data <= i_SPS_hist_rd_data(0) + "0000000000000001";
639  SPS_hist_wr_ena <= "1";
640  fill_SPS_hist_state <= WRITE_TO_RAM;
641  end if;
642 
643  when WRITE_TO_RAM =>
644  fill_SPS_hist_state <= IDLE;
645 
646  when RESETTING =>
647  SPS_hist_wr_ena <= "1";
648  SPS_hist_address <= count;
649  SPS_hist_wr_data <= (others=>'0');
650  -- if count = "11111111111111" then
651  if count = "1111111111" then
652  fill_SPS_hist_state <= IDLE;
653  else
654  count := count + '1';
655  fill_SPS_hist_state <= RESETTING;
656  end if;
657 
658  -- When OTHERS =>
659  end case;
660  end if;
661  end if;
662  end process fill_SPS;
663 
664 
665 
669  avg_and_wr_peds: process(clk, avg_peds_ena_i, sram_asic_addr_i, wave_div_NBA,
670  wave_drdy, avg_peds_rd_ena, avg_peds_chn_sel,
671  sram_samp_addr_i)
672  variable chan : integer range 0 to 15 := 0;
673  -- variable asic : integer range 0 to 4 := 0;
674  begin
675  if rising_edge(clk) then
676  Case avg_peds_state is
677 
678  When IDLE =>
679  chan := 0;
680  -- asic := 0;
681  avg_peds_asic_mask <= (others=>'0');
682  if avg_peds_ena_i = "01" then
683  avg_peds_busy <= '1';
684  avg_peds_asic_mask <= "00001";
685  avg_peds_rd_ena <= '1'; --keep high two clocks
686  sram_asic_addr_i <= "000";
687  sram_samp_addr_i <= "0000";
688  avg_peds_chn_sel <= "0000";
689  avg_peds_state <= READ_ONE_MORE;
690  else
691  avg_peds_rd_ena <= '0';
692  avg_peds_busy <= '0';
693  avg_peds_state <= IDLE;
694  end if;
695 
696  When ASIC_LOOP =>
697  avg_peds_chn_sel <= "0000";
698  sram_samp_addr_i <= "0000";
699  -- if asic < 5 then
700  if avg_peds_asic_mask = "00000" then
701  avg_peds_state <= IDLE;
702  else
703  sram_asic_addr_i <= sram_asic_addr_i + "001";
704  -- avg_peds_asic_mask <= (others=>'0');
705  -- avg_peds_asic_mask(asic) <= '1';
706  avg_peds_rd_ena <= '1'; --keep high two clocks
707  avg_peds_state <= READ_ONE_MORE;
708  end if;
709 
710  When CHANNEL_LOOP =>
711  sram_samp_addr_i <= "0000";
712  if chan < 15 then
713  avg_peds_chn_sel <= avg_peds_chn_sel + "0001";
714  avg_peds_rd_ena <= '1'; --keep high two clocks
715  avg_peds_state <= READ_ONE_MORE;
716  else
717  avg_peds_chn_sel <= "0000";
718  chan := 0;
719  avg_peds_asic_mask <= avg_peds_asic_mask(3 downto 0) & '0';
720  -- asic := asic + 1;
721  avg_peds_state <= ASIC_LOOP;
722  end if;
723 
724  When READ_ONE_MORE =>
725  avg_peds_rd_ena <= '1'; --second clock high
726  avg_peds_state <= AVERAGE_EVEN_SAMPLE;
727 
728 
729  When AVERAGE_EVEN_SAMPLE =>
730  avg_peds_rd_ena <= '0'; --two clocks elapsed, set low here.
731  if wave_drdy = '1' then
732  even_ped <= wave_div_NBA;
733  avg_peds_state <= AVERAGE_ODD_SAMPLE;
734  else
735  avg_peds_state <= AVERAGE_EVEN_SAMPLE;
736  end if;
737 
738  When AVERAGE_ODD_SAMPLE =>
739  wr_peds2sram_ena <= '1';
740  odd_ped <= wave_div_NBA;
741  avg_peds_state <= WAIT_PED_WRITER;
742 
743  When WAIT_PED_WRITER =>
744  wr_peds2sram_ena <= '1';
745  if wr_peds2sram_ack = '1' then
746  wr_peds2sram_ena <= '0';
747  if sram_samp_addr_i /= "1111" then
748  sram_samp_addr_i <= sram_samp_addr_i + "0001";
749  avg_peds_rd_ena <= '1'; --keep high two clocks
750  avg_peds_state <= READ_ONE_MORE;
751  else
752  sram_samp_addr_i <= "0000";
753  chan := chan + 1;
754  avg_peds_state <= CHANNEL_LOOP;
755  end if;
756  else
757  avg_peds_state <= WAIT_PED_WRITER;
758  end if;
759 
760  When OTHERS =>
761  avg_peds_state <= IDLE;
762 
763  end case;
764  end if;
765  end process avg_and_wr_peds;
766 
767 
768 
769 
770 --------------------- BEGIN MODULES ---------------------------------------------
771  SPS_RAM : entity work.SPSBlockRAM
772  port map(
773  clka => clk,
774  -- rsta => '0',
775  addra => SPS_hist_address,
776  dina => SPS_hist_wr_data,
777  douta => i_SPS_hist_rd_data(0),
778  wea => SPS_hist_wr_ena
779  );
780 
781 
782 end Behavioral;
783 
784 
785 
786 
787 
788 
789 
790 
791 
792 
793 
794 
795 
796 
797 
798 
799 
800 
ProcWaveform.Behavioral.feat_ext_rd_ena_q1
std_logic := '0' feat_ext_rd_ena_q1
read_wave:
Definition: ProcWaveform.vhd:124
ProcWaveform.rx_features_ack
in rx_features_ackstd_logic := '0'
wires to HitDataSerializer
Definition: ProcWaveform.vhd:73
ProcWaveform.win_samp_start
in win_samp_startslv14( 4 downto 0) :=( others =>( others => '0'))
event info
Definition: ProcWaveform.vhd:60
ProcWaveform.Behavioral.any_ch_hit
std_logic := '0' any_ch_hit
hit_chs_lgc:
Definition: ProcWaveform.vhd:127
klm_scint_pkg
Definition: klm_scint_pkg.vhd:7
ProcWaveform.fifo_rst
out fifo_rststd_logic := '0'
fifo access
Definition: ProcWaveform.vhd:64
ProcWaveform.Behavioral.wave_data
std_logic_vector( 11 downto 0) :=( others => '0') wave_data
ped_sub:
Definition: ProcWaveform.vhd:114
ProcWaveform.avg_peds_ena
in avg_peds_enastd_logic := '0'
wires needed for pedestal measurement
Definition: ProcWaveform.vhd:81
ProcWaveform.Behavioral.average_peds_state_machine
(IDLE,ASIC_LOOP,CHANNEL_LOOP,READ_ONE_MORE,AVERAGE_EVEN_SAMPLE,AVERAGE_ODD_SAMPLE,WAIT_PED_WRITER) average_peds_state_machine
avg_and_wr_peds:
Definition: ProcWaveform.vhd:174
ProcWaveform.ped_sub_ena
in ped_sub_enastd_logic
control registers
Definition: ProcWaveform.vhd:48
ProcWaveform.Behavioral.feat_ext_state_machine
(CHECK_FIFOS_RDY,IDLE,WAIT_VALID,CHECK_VALID,LOOPING_JOBS,WAITING_FIFO_READ_LAG,LOOPING_SAMPLES,CHECK_DONE) feat_ext_state_machine
Extract_Features:
Definition: ProcWaveform.vhd:132
ProcWaveform.Behavioral.b2tt_rst
std_logic_vector( B2TT_RST_PPLN_STGS- 1 downto 0) b2tt_rst
b2tt_rst_ppln
Definition: ProcWaveform.vhd:108
ProcWaveform.Behavioral.tx_features_state_machine
(IDLE,WAIT_TX) tx_features_state_machine
tx_features:
Definition: ProcWaveform.vhd:160
ProcWaveform.Behavioral.feat_ext_ena
std_logic_vector( 1 downto 0) :=( others => '0') feat_ext_ena
proc_fsm_ena_sel:
Definition: ProcWaveform.vhd:120
ProcWaveform.Behavioral.debug_fifo_fill_state_machine
(IDLE,WRITE_CHAN_AND_SAMP,WRITE_ASIC_AND_WINDOW,WRITING,WRITE_LAST_WORD,WRITE_EOF,STOP) debug_fifo_fill_state_machine
wr_debug_wave:
Definition: ProcWaveform.vhd:155
ProcWaveform.Behavioral.fifo_rst_r
std_logic_vector( FIFO_RST_PPLN_STGS- 1 downto 0) :=( others => '0') fifo_rst_r
SC_buffering:
Definition: ProcWaveform.vhd:111
ProcWaveform.Behavioral.fill_SPS_hist_state_machine
(IDLE,READ_RAM,WRITE_TO_RAM,RESETTING) fill_SPS_hist_state_machine
fill_SPS:
Definition: ProcWaveform.vhd:165
ProcWaveform.sps_reset
in sps_resetstd_logic := '0'
signals for measuring single-photon spectra
Definition: ProcWaveform.vhd:93
ProcWaveform.busy
out busystd_logic := '0'
status registers
Definition: ProcWaveform.vhd:55