Processes
PROCESS_2	( clk , ena )
PROCESS_3	( clk , first_dig_win )
PROCESS_4	( clk , ena_i , ena , first_dig_win_i , win_samp_start_asic , asic_mask , dig_busy , BUS_RD_WINSEL_i , i_win_samp_start_asic , shift_busy , last_dig_win )

Types
digitize_and_shift_out_window_data	( IDLE , WAIT_DIG_BUSY_TO_COME_UP , WAIT_DIG_WINDOW , WAIT_SHIFT_BUSY_TO_COME_UP , WAIT_SHIFT_OUT )

Signals
digNshift_state	digitize_and_shift_out_window_data := IDLE
ena_i	std_logic := ' 0 '
first_dig_win_i	std_logic_vector ( 8 downto 0 ) := ( others = > ' 0 ' )
BUS_RD_WINSEL_i	std_logic_vector ( 8 downto 0 ) := ( others = > ' 0 ' )
i_win_samp_start_asic	slv14 ( 4 downto 0 ) := ( others = > ( others = > ' 0 ' ) )
shift_ena	std_logic := ' 0 '
shift_asic_mask	std_logic_vector ( 4 downto 0 )
shift_samp_start	slv5 ( 4 downto 0 ) := ( others = > ( others = > ' 0 ' ) )
shift_samp_stop	slv5 ( 4 downto 0 ) := ( others = > ( others = > ' 1 ' ) )
shift_busy	std_logic := ' 0 '
dig_ena	std_logic := ' 0 '
dig_busy	std_logic := ' 0 '

Instantiations
diglgc_i	DigitizingLgcTX <Entity DigitizingLgcTX>
shftwin_i	ShiftOutWindow <Entity ShiftOutWindow>

Detailed Description

The documentation for this class was generated from the following file:

Processes