DigitizeAndShiftOutData.vhd

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
use IEEE.STD_LOGIC_MISC.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
Library work;
use work.klm_scint_pkg.all;

entity DigitizeAndShiftOutData is
    port (
        clk                 : in  std_logic := '0';
        rst                 : in  std_logic := '0';
        ena                 : in  std_logic := '0';
        busy                : out std_logic := '0';

        -- state machine input parameters
        win_samp_start_asic : in  slv14(4 downto 0) := (others => (others=>'0'));
        -- samp_start            : in  slv5(4 downto 0) := (others => "00000");
        asic_mask           : in std_logic_vector(4 downto 0) := (others=>'0');
        first_dig_win       : in std_logic_vector(8 downto 0);
        last_dig_win        : in std_logic_vector(8 downto 0);

        -- wires to ThresholdCheck
        sample_data         : out slv12(14 downto 0) := (others=>"000000000000");
        samples_valid       : out std_logic := '0'; -- samplesel & valid flag
        -- samples_sel         : out std_logic_vector(4 downto 0) := (others=>'0');
        current_asic        : out std_logic_vector(4 downto 0) := "00001";

        -- control registers
        ramp_length         : in std_logic_vector (11 downto 6);
        -- force_test_pattern  : in std_logic := '0';
        t_samp_addr_settle  : in std_logic_vector(3 downto 0) := "0110";-- 6
        t_setup_ss_any      : in std_logic_vector(3 downto 0) := "0110";-- 6
        t_strobe_settle     : in std_logic_vector(3 downto 0) := "0100";-- 4
        t_sr_clk_high       : in std_logic_vector(3 downto 0) := "0010";-- 2
        t_sr_clk_low        : in std_logic_vector(3 downto 0) := "0010";-- 2
        t_sr_clk_strobe     : in std_logic_vector(3 downto 0) := "0110";-- 6
        N_readout_samples   : in std_logic_vector(7 downto 0);
        -- status registers
        DigBusy             : out std_logic := '0';
        ShiftOutWinBusy     : out std_logic := '0';
        ShiftOutSampBusy    : out std_logic := '0';

        -- pins to TargetX
        ---- digitization control
        BUS_RD_ENA          : out std_logic := '0';
        BUS_CLR             : out std_logic := '0';
        BUS_RAMP            : out std_logic := '0';
        BUS_RD_WINSEL       : out std_logic_vector(8 downto 0) := (others=>'0');

        ---- shift register data and control
        BUS_DO              : in  std_logic_vector(14 downto 0) := (others=>'0');
        SR_CLR              : out std_logic := '0';
        SR_CLK              : out std_logic_vector(4 downto 0) := (others=>'0');
        SR_SEL              : out std_logic := '0';
        SAMPLESEL           : out std_logic_vector(4 downto 0) := (others=>'0');
        SAMPLESEL_ANY       : out std_logic_vector(4 downto 0) := (others=>'0')
    );
end DigitizeAndShiftOutData;


architecture Behavioral of DigitizeAndShiftOutData is


    type digitize_and_shift_out_window_data is (
        IDLE,
        WAIT_DIG_BUSY_TO_COME_UP,      -- next_state = (WAIT_DIG_BUSY_TO_COME_UP) or (IDLE)
        WAIT_DIG_WINDOW,
        WAIT_SHIFT_BUSY_TO_COME_UP,
        WAIT_SHIFT_OUT  ---- next_state = WAIT_DIG_BUSY_TO_COME_UP
    );
    signal digNshift_state : digitize_and_shift_out_window_data := IDLE;

    -- internal state machine signals
    signal ena_i                : std_logic := '0';
    -- signal count                : std_logic_vector(7 downto 0) := "00000000";
    -- signal earliest_win_samp            : std_logic_vector(8 downto 0) := (others=>'0');
    signal first_dig_win_i          : std_logic_vector(8 downto 0) := (others=>'0');
    signal BUS_RD_WINSEL_i      : std_logic_vector(8 downto 0) := (others=>'0');
    signal i_win_samp_start_asic : slv14(4 downto 0) := (others => (others=>'0'));

    -- ShiftOutWindow signals
    signal shift_ena       : std_logic := '0';
    signal shift_asic_mask   : std_logic_vector(4 downto 0);
    signal shift_samp_start : slv5(4 downto 0) := (others=>(others=>'0'));
    signal shift_samp_stop  : slv5(4 downto 0) := (others=>(others=>'1'));
    signal shift_busy      : std_logic := '0';


    -- DigitizingLgcTX signals
    signal dig_ena         : std_logic := '0';
    signal dig_busy        : std_logic := '0';

----------------------------------------
begin

    BUS_RD_WINSEL <= BUS_RD_WINSEL_i;
    ShiftOutWinBusy <= shift_busy;
    DigBusy <= dig_busy;

    DigLgc_i : entity work.DigitizingLgcTX
        port map (
        clk                 => clk,
        rst                 => rst,
        ena                 => dig_ena,
        busy                => dig_busy,

        -- control registers
        -- force_test_pattern  => force_test_pattern,
        ramp_length         => ramp_length,

        -- pins to TargetX
        BUS_RD_ENA          => BUS_RD_ENA,
        BUS_CLR             => BUS_CLR,
        BUS_RAMP            => BUS_RAMP
    );


    ShftWin_i : entity work.ShiftOutWindow
    port map (
        clk                => clk,
        rst                => rst,
        ena                => shift_ena,
        busy               => shift_busy,
        -- force_test_pattern => force_test_pattern,
        t_samp_addr_settle => t_samp_addr_settle,
        t_setup_ss_any     => t_setup_ss_any,
        t_strobe_settle    => t_strobe_settle,
        t_sr_clk_high      => t_sr_clk_high  ,
        t_sr_clk_low       => t_sr_clk_low   ,
        t_sr_clk_strobe    => t_sr_clk_strobe ,
        ShiftOutSampBusy   => ShiftOutSampBusy,
        asic_mask          => shift_asic_mask,
        samp_start_asic    => shift_samp_start,
        samp_stop_asic     => shift_samp_stop,
        samples_valid      => samples_valid,
        -- sample_sel         => sample_sel,
        sample_data        => sample_data,
        current_asic       => current_asic,
        BUS_DO             => BUS_DO,
        SR_CLR             => SR_CLR,
        SR_CLK             => SR_CLK,
        SR_SEL             => SR_SEL,
        SAMPLESEL          => SAMPLESEL,
        SAMPLESEL_ANY      => SAMPLESEL_ANY
    );


    --detect start rising edge
    process (clk, ena)
    begin
        if rising_edge(clk) then
            ena_i <= ena;
        end if;
    end process;


    process (clk, first_dig_win)
    begin
        if rising_edge(clk) then
            first_dig_win_i <= first_dig_win;
        end if;
    end process;



    process(clk, ena_i, ena, first_dig_win_i, win_samp_start_asic, asic_mask,
            dig_busy, BUS_RD_WINSEL_i, i_win_samp_start_asic, shift_busy, last_dig_win)
        variable i_asic_mask : std_logic_vector(4 downto 0);
    begin
        if rising_edge(clk) then
            if rst = '1' then
                digNshift_state <= IDLE;
            else
                Case digNshift_state is
                    
                    When IDLE =>
                        shift_asic_mask <= (others=>'0');
                        shift_samp_stop <= (others=>"11111");
                        if ( ena_i = '0' and ena = '1' ) then
                            busy <= '1';
                            BUS_RD_WINSEL_i <= first_dig_win_i; -- set initial window address
                            -- count <= "00100000" - ("000" & samp_start); -- num samps shifted out in first win
                            i_win_samp_start_asic <= win_samp_start_asic;
                            -- samp_start_asic <= samp_start;
                            dig_ena <= '1';
                            i_asic_mask := asic_mask;
                            digNshift_state <= WAIT_DIG_BUSY_TO_COME_UP;
                        else
                            -- count <= (others=>'0');
                            i_win_samp_start_asic <= (others=>(others=>'0'));
                            BUS_RD_WINSEL_i <= (others=>'0');
                            shift_ena <= '0';
                            dig_ena <= '0';
                            busy <= '0';
                            digNshift_state <= IDLE;
                        end if;
                    
                    When WAIT_DIG_BUSY_TO_COME_UP =>
                        dig_ena <= '1';
                        if dig_busy = '1' then
                            digNshift_state <= WAIT_DIG_WINDOW;
                        else
                            digNshift_state <= WAIT_DIG_BUSY_TO_COME_UP;
                        end if;
                    
                    When WAIT_DIG_WINDOW =>
                        dig_ena <= '0';
                        if dig_busy = '1' then
                            digNshift_state <= WAIT_DIG_WINDOW;
                        else
                            digNshift_state <= WAIT_SHIFT_BUSY_TO_COME_UP;
                            shift_ena <= '1';
                            for i in 0 to 4 loop
                                if i_asic_mask(i) = '1' then
                                    
                                    if BUS_RD_WINSEL_i & "11111" - i_win_samp_start_asic(i) < N_readout_samples then
                                        shift_asic_mask(i) <= '1';
                                    else
                                        shift_asic_mask(i) <= '0';
                                    end if;
                                    
                                    if BUS_RD_WINSEL_i = i_win_samp_start_asic(i)(13 downto 5) then
                                        shift_samp_start(i) <= i_win_samp_start_asic(i)(4 downto 0);
                                    else
                                        shift_samp_start(i) <= "00000";
                                    end if;
                                    
                                    if BUS_RD_WINSEL_i = i_win_samp_start_asic(i)(13 downto 5) + "000000" & N_readout_samples(7 downto 5) then
                                        shift_samp_stop(i) <= "11111" - i_win_samp_start_asic(i)(4 downto 0);
                                    else
                                        shift_samp_stop(i) <= "11111";
                                    end if;
                                    
                                end if;
                            end loop;
                        end if;
                    
                    When WAIT_SHIFT_BUSY_TO_COME_UP =>
                        shift_ena <= '1';
                        if shift_busy = '1' then
                            digNshift_state <= WAIT_SHIFT_OUT;
                        else
                            digNshift_state <= WAIT_SHIFT_BUSY_TO_COME_UP;
                        end if;
                    
                    When WAIT_SHIFT_OUT =>
                        shift_ena <= '0';
                        if shift_busy = '1' then
                            digNshift_state <= WAIT_SHIFT_OUT;
                        else
                            BUS_RD_WINSEL_i <= BUS_RD_WINSEL_i + "000000001"; -- automatically rolls over at window 512
                            -- shift_samp_start <= "00000";
                            if BUS_RD_WINSEL_i /= last_dig_win then
                                dig_ena <= '1';
                                digNshift_state <= WAIT_DIG_BUSY_TO_COME_UP;
                            else
                                dig_ena <= '0';
                                busy <= '0';
                                digNshift_state <= IDLE;
                            end if;
                            
                        end if;
                    
                    When OTHERS =>
                        digNshift_state <= IDLE;
                    
                end case;
            end if;
        end if;
    end process;


end Behavioral;