Inheritance diagram for ShiftOutWindow:

Ports
clk	in std_logic := ' 0 '
rst	in std_logic := ' 0 '
ena	in std_logic := ' 0 '
busy	out std_logic := ' 0 '
t_samp_addr_settle	in std_logic_vector ( 3 downto 0 ) := " 0110 "
t_setup_ss_any	in std_logic_vector ( 3 downto 0 ) := " 0110 "
t_strobe_settle	in std_logic_vector ( 3 downto 0 ) := " 0100 "
t_sr_clk_high	in std_logic_vector ( 3 downto 0 ) := " 0010 "
t_sr_clk_low	in std_logic_vector ( 3 downto 0 ) := " 0010 "
t_sr_clk_strobe	in std_logic_vector ( 3 downto 0 ) := " 0110 "
ShiftOutSampBusy	out std_logic := ' 0 '
asic_mask	in std_logic_vector ( 4 downto 0 ) := ( others = > ' 0 ' )
samp_start_asic	in slv5 ( 4 downto 0 ) := ( others = > ( others = > ' 0 ' ) )
samp_stop_asic	in slv5 ( 4 downto 0 ) := ( others = > ( others = > ' 1 ' ) )
samples_valid	out std_logic := ' 0 '
sample_data	out slv12 ( 14 downto 0 ) := ( others = > " 000000000000 " )
current_asic	out std_logic_vector ( 4 downto 0 ) := " 00001 "
BUS_DO	in std_logic_vector ( 14 downto 0 ) := ( others = > ' 0 ' )
SR_CLR	out std_logic := ' 0 '
SR_CLK	out std_logic_vector ( 4 downto 0 ) := ( others = > ' 0 ' )
SR_SEL	out std_logic := ' 0 '
SAMPLESEL	out std_logic_vector ( 4 downto 0 ) := ( others = > ' 0 ' )
SAMPLESEL_ANY	out std_logic_vector ( 4 downto 0 ) := ( others = > ' 0 ' )

Detailed Description

Shift Out TargetX Window Data. Chris Ketter. 09/18/2019.

Loops over all ASICs declared in asic_mask. Enables ShiftOutSample.vhd once for each sample in the range from samp_start[asic] to samp_stop[asic].

samp_start[asic] <  samp_stop[asic],
samp_start[asic] >= 0,
samp_stop[asic]  <  32

Definition at line 23 of file ShiftOutWindow.vhd.

The documentation for this class was generated from the following file:

Entities